NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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33.3.6 Communication Interfaces
Table 33-15. LPSPIn Signal Descriptions
Chip signal name Module signal
name
Description I/O
LPSPI n _SOUT SOUT Serial Data Out O
LPSPI n _SIN SIN Serial Data In I
LPSPI n _SCK SCK Serial Clock I/O
LPSPI n _PCS[3:0] PCS[3:0] Peripheral Chip Select 0-3 I/O
Table 33-16. LPI2Cn Signal Descriptions
Chip signal name Module signal
name
Description I/O
LPI2C n _SCL SCL Bidirectional serial clock line of the I2C system. I/O
LPI2C n _SDA SDA Bidirectional serial data line of the I2C system. I/O
LPI2C n _HREQ HREQ Host request, can initiate an LPI2C master transfer if asserted and
the I2C bus is idle. I
LPI2C n _SCLS SCLS Secondary I2C clock line. I/O
LPI2C n _SDAS SDAS Secondary I2C data line. I/O
Table 33-17. LPUARTn Signal Descriptions
Chip signal name Module signal
name
Description I/O
LPUART n _TX LPUART_TX Transmit data I/O
LPUART n _RX LPUART_RX Receive data I
LPUART n _CTS LPUART_CTS Clear to send I
LPUART n _RTS LPUART_RTS Request to send O
Table 33-18. FlexIO Signal Descriptions
Chip signal name Module signal
name
Description I/O
FXIO_D[7:0] FXIO_D[7:0] Bidirectional FlexIO Shifter and Timer pin inputs/outputs I/O
Module Signal Description Tables
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
688 NXP Semiconductors