NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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DMA_EARS field descriptions (continued)
Field Description
0 Disable asynchronous DMA request for channel 1
1 Enable asynchronous DMA request for channel 1.
0
EDREQ_0
Enable asynchronous DMA request in stop mode for channel 0.
0 Disable asynchronous DMA request for channel 0.
1 Enable asynchronous DMA request for channel 0.
13.3.21 Channel n Priority Register (DMA_DCHPRIn)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities
are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher
priority, then 2, 3, etc. Software must program the channel priorities with unique values;
otherwise, a configuration error is reported. The range of the priority value is limited to
the values of 0 through 7.
Address: 4000_8000h base + 100h (1d × i), where i=0d to 7d
Bit 7 6 5 4 3 2 1 0
Read
ECP DPA
0
CHPRI
Write
Reset 0 0 0 0 0 * * *
* Notes:
CHPRI field: See bit field description. •
DMA_DCHPRIn field descriptions
Field Description
7
ECP
Enable Channel Preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
6
DPA
Disable Preempt Ability.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
5–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CHPRI Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number
for each priority register, that is, DCHPRI7[CHPRI] = 0b111.
Memory map/register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
226 NXP Semiconductors