NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1240 / 1325

47.3.17 Shifter Buffer N Bit Byte Swapped Register
(FLEXIO_SHIFTBUFBBSn)
.
Address: 4005_A000h base + 380h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SHIFTBUFBBS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXIO_SHIFTBUFBBSn field descriptions
Field Description
SHIFTBUFBBS Shift Buffer
Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads
return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }.
47.3.18 Timer Control N Register (FLEXIO_TIMCTLn)
.
Address: 4005_A000h base + 400h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRGSEL
TRGPOL
TRGSRC
0
PINCFG
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PINSEL
PINPOL
0
TIMOD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXIO_TIMCTLn field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
TRGSEL
Trigger Select
The valid values for TRGSEL will depend on the FLEXIO_PARAM register.
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1240 NXP Semiconductors