NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1241 / 1325

FLEXIO_TIMCTLn field descriptions (continued)
Field Description
• When TRGSRC = 1, the valid values for N will depend on PIN, TIMER, SHIFTER fields in the
FLEXIO_PARAM register.
• When TRGSRC = 0, the valid values for N will depend on TRIGGER field in FLEXIO_PARAM
register.
Refer to the chip configuration section for external trigger selection.
The internal trigger selection is configured as follows:
{N,00} pin 2N input
{N,01} shifter N status flag
{N,10} pin 2N+1 input
{N,11} timer N trigger output
23
TRGPOL
Trigger Polarity
0 Trigger active high
1 Trigger active low
22
TRGSRC
Trigger Source
0 External trigger selected
1 Internal trigger selected
21–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17–16
PINCFG
Timer Pin Configuration
00 Timer pin output disabled
01 Timer pin open drain or bidirectional output enable
10 Timer pin bidirectional output data
11 Timer pin output
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
PINSEL
Timer Pin Select
Selects which pin is used by the Timer input or output.
7
PINPOL
Timer Pin Polarity
0 Pin is active high
1 Pin is active low
6–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TIMOD Timer Mode
In 8-bit counter mode, the lower 8-bits of the counter and compare register are used to configure the baud
rate of the timer shift clock and the upper 8-bits are used to configure the shifter bit count.
In 8-bit PWM mode, the lower 8-bits of the counter and compare register are used to configure the high
period of the timer shift clock and the upper 8-bits are used to configure the low period of the timer shift
clock. The shifter bit count is configured using another timer or external signal.
In 16-bit counter mode, the full 16-bits of the counter and compare register are used to configure either the
baud rate of the shift clock or the shifter bit count.
00 Timer Disabled.
Table continues on the next page...
Chapter 47 Flexible I/O (FlexIO)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1241