NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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44.3.7 Configuration Register 0 (LPSPIx_CFGR0)
Address: Base a 20h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RDMO
CIRFIFO
0
HRSEL HRPOL
HREN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPSPIx_CFGR0 field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
RDMO
Receive Data Match Only
When enabled, all received data that does not cause DMF to set is discarded. Once DMF is set, the
RDMO configuration is ignored. When disabling RDMO, clear RDMO before clearing DMF to ensure no
receive data is lost.
0 Received data is stored in the receive FIFO as normal.
1 Received data is discarded unless the DMF is set.
8
CIRFIFO
Circular FIFO Enable
When enabled, the transmit FIFO read pointer is saved to a temporary register. The transmit FIFO will be
emptied as normal, but once the LPSPI is idle and the transmit FIFO is empty, then the read pointer value
will be restored from the temporary register. This will cause the contents of the transmit FIFO to be cycled
through repeatedly.
0 Circular FIFO is disabled.
1 Circular FIFO is enabled.
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
HRSEL
Host Request Select
Selects the source of the host request input. When the host request function is enabled with the
LPSPI_HREQ pin, the LPSPI_PCS[1] function is disabled.
0 Host request input is pin LPSPI_HREQ.
1 Host request input is input trigger.
1
HRPOL
Host Request Polarity
Table continues on the next page...
Memory Map and Registers
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1102 NXP Semiconductors