NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1005 / 1325

• SW Synchronization for Inverting (if it is necessary): SWINVC = [0/1] and
INVC = [0/1].
• SW Synchronization for SWOM (always): SWOM = 1. No enable the SW
Synchronization for write buffers (because the writes to registers with write
buffer are done using CLKS[1:0] = 2’b00): SWWRBUF = 0 and CNTINC =
0 .
• SW Synchronization for counter reset (always): SWRSTCNT = 1.
• Enhanced synchronization (always): SYNCMODE = 1.
• If the SWOC is used (SWSOC = 1 and SWOC = 1), then write to SWOCTRL
register.
• If the Inverting is used (SWINVC = 1 and INVC = 1), then write to INVCTRL
register.
• Write to OUTMASK to enable the masked channels.
7. Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 =
0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0)
8. Write to PWM_EN to enable the PWM outputs.
39.9 Usage Guide
39.9.1 FTM Interrupts
The FlexTimer has multiple sources of interrupt. However, these sources are OR'd
together to generate a single interrupt request to the interrupt controller. When an FTM
interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the
exact interrupt source.
39.9.2 FTM Hall sensor support
For 3 phase motor control sensor-ed applications the use of Hall sensors, generally 3
sensors placed 120 degrees apart around the rotor, are deployed to detect position and
speed. Each of the 3 sensors provides a pulse that applied to an input capture pin, can
then be analyzed and both speed and position can be deduced. This device has two 2-
channel FTMs. (FTM1 and FTM2) and thus provides 4 input capture pins. To simplify
the calculations required by the CPU on each hall sensor's input, if all 3 inputs are
"exclusively OR'd" into one timer channel and the free running counter is refreshed on
every edge then this can simplify the speed calculation.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1005