NXP Semiconductors KE1xF Series, Reference Manual, Page: 68 / 1483

SIM memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_800C FTM Option Register 0 (SIM_FTMOPT0) 32 R/W 0000_0000h 5.2.2/70
4004_8018 ADC Options Register (SIM_ADCOPT) 32 R/W 0000_0000h 5.2.3/72
4004_801C FTM Option Register 1 (SIM_FTMOPT1) 32 R/W 0000_0000h 5.2.4/74
4004_8024 System Device Identification Register (SIM_SDID) 32 R See section 5.2.5/76
4004_8040 Platform Clock Gating Control Register (SIM_PLATCGC) 32 R/W 0000_0007h 5.2.6/77
4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 5.2.7/78
4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 5.2.8/81
4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 5.2.9/82
4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 5.2.10/82
4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 5.2.11/83
4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 5.2.12/83
4004_8068 System Clock Divider Register 4 (SIM_CLKDIV4) 32 R/W 1000_0000h 5.2.13/84
4004_806C Miscellaneous Control register (SIM_MISCTRL) 32 R/W 0000_0000h 5.2.14/85
5.2.1 Chip Control register (SIM_CHIPCTL)
SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock,
clock out source, PDB back-to-back mode and ADC interleave channel.
Address: 4004_8000h base + 4h offset = 4004_8004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
RTC_CLKSEL
PWT_CLKSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CAN_FLT_CLK_
SEL
0
PDB_
BB_
SEL
TRACECLK_SEL
0 0
CLKOUTSEL
CLKOUTDIV
ADC_INTERLEAVE_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
68 NXP Semiconductors