NXP Semiconductors KE1xF Series, Reference Manual, Page: 84 / 1483

5.2.13 System Clock Divider Register 4 (SIM_CLKDIV4)
Address: 4004_8000h base + 68h offset = 4004_8068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRACEDIVEN
0
W
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRACEDIV
TRACEFRAC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_CLKDIV4 field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
TRACEDIVEN
Debug Trace Divider Control
This bit controls the Debug Trace Divider.
0 Debug trace divider disabled
1 Debug trace divider enabled
27–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–1
TRACEDIV
Trace clock divider divisor
NOTE
To configure TRACEDIV, the user must disable TRACEDIVEN at first,
and then enable it after setting TRACEDIV.
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock × [(TR1)/(T1)].
0
TRACEFRAC
Trace clock divider fraction
NOTE
To configure TRACEDIV and TRACEFRAC, the user must clear
TRACEDIVEN at first to disable the trace clock divide function.
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider
input clock × [(TR1)/(T1)].
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
84 NXP Semiconductors