NXP Semiconductors KE1xF Series, Reference Manual, Page: 70 / 1483

SIM_CHIPCTL field descriptions (continued)
Field Description
5–4
CLKOUTDIV
CLKOUT divider
00 no divider
01 div 2
10 div 4
11 div 8
ADC_
INTERLEAVE_
EN
ADC interleave channel enable
Select ADC interleave pins. Bit 3 to 0 are for PTB14, PTB13, PTB1 and PTB0 respectively.
0000 No interleave channel
Bit 3: PTB14 to ADC1_SE9 and ADC2_SE9
Bit 2: PTB13 to ADC1_SE8 and ADC2_SE8
Bit 1: PTB1 to ADC0_SE5 and ADC1_SE15
Bit 0: PTB0 to ADC0_SE4 and ADC1_SE14
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)
Address: 4004_8000h base + Ch offset = 4004_800Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FTM3CLKSE
L
FTM2CLKSE
L
FTM1CLKSE
L
FTM0CLKSE
L
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FTM3FLTxSEL
0
FTM2FLTxSEL
0
FTM1FLTxSEL
0
FTM0FLTxSEL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_FTMOPT0 field descriptions
Field Description
31–30
FTM3CLKSEL
FTM3 External Clock Pin Select
Selects the external pin used to drive the clock to the FTM3 module.
NOTE: The selected pin must also be configured for the FTM external clock function through the
appropriate Pin Control Register in the Port Control module.
00 FTM3 external clock driven by TCLK0 pin.
01 FTM3 external clock driven by TCLK1 pin.
10 FTM3 external clock driven by TCLK2 pin.
11 No clock input
29–28
FTM2CLKSEL
FTM2 External Clock Pin Select
Selects the external pin used to drive the clock to the FTM2 module.
Table continues on the next page...
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
70 NXP Semiconductors