NXP Semiconductors K32 L2A Series, Reference Manual, Page: 855 / 1379

MMDVSQ memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F000_4000 Dividend Register (MMDVSQ0_DEND) 32 R/W Undefined 32.3.1/855
F000_4004 Divisor Register (MMDVSQ0_DSOR) 32 R/W Undefined 32.3.2/855
F000_4008 Control/Status Register (MMDVSQ0_CSR) 32 R/W See section 32.3.3/857
F000_400C Result Register (MMDVSQ0_RES) 32 R/W Undefined 32.3.4/860
F000_4010 Radicand Register (MMDVSQ0_RCND) 32 W Undefined 32.3.5/860
32.3.1 Dividend Register (MMDVSQx_DEND)
This register is loaded with the input dividend operand before a divide operation is
initiated. The register is updated by the MMDVSQ hardware during the execution of a
divide or square root calculation. Any memory access (read or write) of the DEND
register while the module is busy during a calculation causes the access to be stalled
(using wait states) until the calculation completes.
Address: F000_4000h base + 0h offset = F000_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DIVIDEND
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
MMDVSQx_DEND field descriptions
Field Description
DIVIDEND Dividend
This is the input dividend operand for divide calculations.
32.3.2 Divisor Register (MMDVSQx_DSOR)
This register is loaded with the input divisor operand before a divide operation is
initiated. If CSR[DFS] = 0, a write to this register inititates a divide operation. Any
memory access (read or write) of the DSOR register while the module is busy during a
calculation causes the access to be stalled (using wait states) until the calculation
completes.
Chapter 32 Memory-Mapped Divide and Square Root (MMDVSQ)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 855