NXP Semiconductors K32 L2A Series, Reference Manual, Page: 857 / 1379

32.3.3 Control/Status Register (MMDVSQx_CSR)
This register defines the operating configuration of divide operations and provides status
information. The upper 3 bits provide busy status indicators, while the low-order byte
defines the configuration for divide operations. The read-only status bits in CSR[31:29]
are valid for both divide and square root operations; the configuration and status bit in
CSR[5:0] are only valid for divides. A memory write access of the CSR register while the
module is busy during a calculation causes the access to be stalled (using wait states)
until the calculation completes.
Address: F000_4000h base + 8h offset = F000_4008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BUSY
DIV
SQRT
0
W
Reset 0 x* x* 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DFS
DZ
DZE REM
USGN
0
W
SRT
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
x = Undefined at reset. •
MMDVSQx_CSR field descriptions
Field Description
31
BUSY
BUSY
This read-only bit is asserted when the MMDVSQ is performing a divide or square root. When an
operation is initiated, the hardware sets this flag. It remains asserted until the operation completes and the
Table continues on the next page...
Chapter 32 Memory-Mapped Divide and Square Root (MMDVSQ)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 857