NXP Semiconductors K32 L2A Series, Reference Manual, Page: 709 / 1379

LPI2Cx_MCFGR0 field descriptions (continued)
Field Description
Configures the polarity of the host request input pin.
0 Active low.
1 Active high.
0
HREN
Host Request Enable
When enabled, the LPI2C master will only initiate a START condition if the host request input is asserted
and the bus is idle. A repeated START is not affected by the host request.
0 Host request input is disabled.
1 Host request input is enabled.
27.2.8 Master Configuration Register 1 (LPI2Cx_MCFGR1)
The MCFGR1 should only be written when the I2C Master is disabled.
Address: Base a 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
PINCFG
0
MATCFG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIMECFG
IGNACK
AUTOSTOP
0
PRESCALE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MCFGR1 field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26–24
PINCFG
Pin Configuration
Configures the pin mode.
000 LPI2C configured for 2-pin open drain mode.
001 LPI2C configured for 2-pin output only mode (ultra-fast mode).
010 LPI2C configured for 2-pin push-pull mode.
011 LPI2C configured for 4-pin push-pull mode.
100 LPI2C configured for 2-pin open drain mode with separate LPI2C slave.
Table continues on the next page...
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 709