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LPI2Cx_MCFGR1 field descriptions (continued)
Field
Description
101
LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave.
110
LPI2C configured for 2-pin push-pull mode with separate LPI2C slave.
111
LPI2C configured for 4-pin push-pull mode (inverted outputs).
23–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
MATCFG
Match Configuration
Configures the condition that will cause the DMF to set.
000
Match disabled.
001
Reserved.
010
Match enabled (1st data word equals MATCH0 OR MATCH1).
011
Match enabled (any data word equals MATCH0 OR MATCH1).
100
Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).
101
Match enabled (any data word equals MATCH0 AND next data word equals MATCH1).
110
Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1).
111
Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
TIMECFG
Timeout Configuration
0
Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout.
1
Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout.
9
IGNACK
When set, the received NACK field is ignored and assumed to be ACK. This bit is required to be set in
Ultra-Fast Mode.
0
LPI2C Master will receive ACK and NACK normally.
1
LPI2C Master will treat a received NACK as if it was an ACK.
8
AUTOSTOP
Automatic STOP Generation
When enabled, a STOP condition is generated whenever the LPI2C master is busy and the transmit FIFO
is empty. The STOP condition can also be generated using a transmit FIFO command.
0
No effect.
1
STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is
busy.
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
PRESCALE
Prescaler
Configures the clock prescaler used for all LPI2C master logic, except the digital glitch filters.
000
Divide by 1.
001
Divide by 2.
010
Divide by 4.
011
Divide by 8.
100
Divide by 16.
101
Divide by 32.
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
710
NXP Semiconductors
Summary of Contents for K32 L2A Series
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Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...
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