NXP Semiconductors K32 L2A Series, Reference Manual, Page: 559 / 1379

22.2.1.21.1 Address
Register Offset
TIMCFG0 400CA480h
TIMCFG1 400CA484h
TIMCFG2 400CA488h
TIMCFG3 400CA48Ch
TIMCFG4 400CA490h
TIMCFG5 400CA494h
TIMCFG6 400CA498h
TIMCFG7 400CA49Ch
22.2.1.21.2 Function
The options to enable or disable the timer using the Timer N-1 enable or disable are
reserved when N is evenly divisible by 4 (eg: Timer 0).
22.2.1.21.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
TIMOUT
0
TIMDEC
0
TIMRST
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
TIMDIS
0
TIMENA
0
TSTOP
0
TSTA
RT
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.2.1.21.4 Fields
Field Function
31-26
—
25-24
TIMOUT
Timer Output
Configures the initial state of the Timer Output and whether it is affected by the Timer reset.
00b - Timer output is logic one when enabled and is not affected by timer reset
01b - Timer output is logic zero when enabled and is not affected by timer reset
10b - Timer output is logic one when enabled and on timer reset
11b - Timer output is logic zero when enabled and on timer reset
23-22
Table continues on the next page...
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 559