NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1350 / 1379

53.2.2 VREF Status and Control Register (VREF_SC)
This register contains the control bits that enable the internal voltage reference and select
the buffer mode to be used.
Address: 4007_2000h base + 1h offset = 4007_2001h
Bit 7 6 5 4 3 2 1 0
Read
VREFEN REGEN ICOMPEN TRESEN TMUXEN
VREFST
MODE_LV
Write
Reset 0 0 0 0 0 0 0 0
VREF_SC field descriptions
Field Description
7
VREFEN
Internal Voltage Reference enable
Enables the bandgap reference within the Voltage Reference module.
NOTE: After the VREF is enabled, turning off the clock to the VREF module via the corresponding clock
gate register will not disable the VREF. VREF must be disabled using this VREFEN bit.
0 The module is disabled.
1 The module is enabled.
6
REGEN
Regulator enable
Enables the internal 1.75 V regulator to produce a constant internal voltage supply in order to reduce the
sensitivity to external supply noise and variation. If it is desired to keep the regulator enabled in very low
power modes, refer to the Chip Configuration details to see how this can be achieved.
REGEN bit should be written to 1 to achieve the performance stated in the data sheet.
NOTE: See section "Internal voltage regulator" for details on the required sequence to enable the internal
regulator.
0 Internal 1.75 V regulator is disabled.
1 Internal 1.75 V regulator is enabled.
5
ICOMPEN
Second order curvature compensation enable
ICOMPEN bit should be written to 1 to achieve the performance stated in the data sheet.
0 Disabled
1 Enabled
4
TRESEN
Test second order curvature compensation enable
TRESEN bit is accessible only in functional test mode.
0 Disabled
1 Enabled
3
TMUXEN
Test MUX enable
Table continues on the next page...
Memory Map and Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1350 NXP Semiconductors