NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1313 / 1379

51.4.9 Interrupt Status register (USBx_ISTAT)
Contains fields for each of the interrupt sources within the USB Module. Each of these
fields are qualified with their respective interrupt enable bits. All fields of this register are
logically OR'd together along with the OTG Interrupt Status Register (OTGSTAT) to
form a single interrupt source for the processor's interrupt controller. After an interrupt
bit has been set it may only be cleared by writing a one to the respective interrupt bit.
This register contains the value of 0x00 after a reset.
Address: 4005_5000h base + 80h offset = 4005_5080h
Bit 7 6 5 4 3 2 1 0
Read STALL ATTACH RESUME SLEEP TOKDNE SOFTOK ERROR USBRST
Write w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
USBx_ISTAT field descriptions
Field Description
7
STALL
Stall Interrupt
In Device mode this bit is asserted when a STALL handshake is sent by the SIE.
In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake
phase of a USB transaction.This interrupt can be used to determine whether the last USB transaction was
completed successfully or stalled.
6
ATTACH
Attach Interrupt
This field is set when the USB Module detects an attach of a USB device. This field is only valid if
CTL[HOSTMODEEN]=1. This interrupt signifies that a peripheral is now present and must be configured; it
is asserted if there have been no transitions on the USB for 2.5 µs and the current bus state is not SE0."
0 No Attach is detected since the last time the ATTACH bit was cleared.
1 A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than
2.5 µs).
5
RESUME
This bit is set when a K-state is observed on the DP/DM signals for 2.5 µs. When not in suspend mode
this interrupt must be disabled.
4
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms. The sleep timer is
reset by activity on the USB bus.
3
TOKDNE
This bit is set when the current token being processed has completed. The processor must immediately
read the STATUS (STAT) register to determine the EndPoint and BD used for this token. Clearing this bit
(by writing a one) causes STAT to be cleared or the STAT holding register to be loaded into the STAT
register.
2
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
In Host mode this field is set when the SOF threshold is reached (MISCCTRL[SOFBUSSET]=0), or when
the SOF counter reaches 0 (MISCCTRL[SOFBUSSET]=1), so that software can prepare for the next SOF.
Table continues on the next page...
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1313