NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1314 / 1379

USBx_ISTAT field descriptions (continued)
Field Description
1
ERROR
This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur. The
processor must then read the ERRSTAT register to determine the source of the error.
0
USBRST
This bit is set when the USB Module has decoded a valid USB reset. This informs the processor that it
should write 0x00 into the address register and enable endpoint 0. USBRST is set after a USB reset has
been detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been
removed and then reasserted.
51.4.10 Interrupt Enable register (USBx_INTEN)
Contains enable fields for each of the interrupt sources within the USB Module. Setting
any of these bits enables the respective interrupt source in the ISTAT register. This
register contains the value of 0x00 after a reset.
Address: 4005_5000h base + 84h offset = 4005_5084h
Bit 7 6 5 4 3 2 1 0
Read
STALLEN ATTACHEN RESUMEEN SLEEPEN TOKDNEEN SOFTOKEN ERROREN USBRSTEN
Write
Reset
0 0 0 0 0 0 0 0
USBx_INTEN field descriptions
Field Description
7
STALLEN
STALL Interrupt Enable
0 Diasbles the STALL interrupt.
1 Enables the STALL interrupt.
6
ATTACHEN
ATTACH Interrupt Enable
0 Disables the ATTACH interrupt.
1 Enables the ATTACH interrupt.
5
RESUMEEN
RESUME Interrupt Enable
0 Disables the RESUME interrupt.
1 Enables the RESUME interrupt.
4
SLEEPEN
SLEEP Interrupt Enable
0 Disables the SLEEP interrupt.
1 Enables the SLEEP interrupt.
3
TOKDNEEN
TOKDNE Interrupt Enable
0 Disables the TOKDNE interrupt.
1 Enables the TOKDNE interrupt.
2
SOFTOKEN
SOFTOK Interrupt Enable
0 Disbles the SOFTOK interrupt.
1 Enables the SOFTOK interrupt.
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1314 NXP Semiconductors