NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-16 Freescale Semiconductor
20.3.4 Configuration/Status Register 3 (CSR3)
CSR3 contains the BDM flash clock divider (BFCDIV) value in a format similar to HCS08 devices.
There are multiple ways to reference CSR3. They are summarized in Table 20-10 .
6
APCDIV16
Automatic PC synchronization divide cycle counts by 16. This bit divides the cycle counts for automatic SYNC_PC
command insertion by 16. See the APCSC and APCENB field descriptions.
5 Reserved, must be cleared.
4–3
PSTBRM
PST trace buffer recording mode. Defines the trace buffer recording mode. The start and stop recording conditions
are defined by the PSTBSS field.
00 Non-obstrusive, normal recording mode
01 Obtrusive, normal recording
10 Non-obtrusive, PC profile recording. Automatic PC synchronization must be enabled (see XCSR[APCSC,
APCENB], CSR2[APCDIV16], and CSR[BTB]).
11 Obtrusive, PC profile recording. Automatic PC synchronization must be enabled (see XCSR[APCSC,
APCENB], CSR2[APCDIV16], and CSR[BTB]).
The terms obtrusive and non-obtrusive are defined as:
• Non-obtrusive—The core is not halted. The PST trace buffer is overwritten unless a PSTB start/stop
combination results in less than or equal to 64 PSTB captures.
• Obtrusive—The core is halted when the PSTB trace buffer reaches its full level (full before overwriting). The
PSTB trace buffer contents are available by the BDM PSTB_READ commands. The PSTB trace buffer write
address resets and the CPU resumes upon a BDM GO command.
2–0
PSTBSS
PST trace buffer start/stop definition. Specifies the start and stop conditions for PST trace buffer recording. In
certain cases, the start and stop conditions are defined by the breakpoint registers. The remaining breakpoint
registers are available for trigger configurations.
Table 20-10. CSR3 Reference Summary
Method Reference Details
READ_CSR3_BYTE Reads CSR3[31
–
24] from the BDM interface. Available in all modes.
WRITE_CSR3_BYTE Writes CSR3[31
–
24] from the BDM interface. Available in all modes.
Table 20-9. CSR2 Field Descriptions (continued)
Field Description
PSTBSS Start Condition Stop Condition
000 Trace buffer disabled, no recording
001 Unconditional recording
010
AB x R{& DBR/DBMR}
PBR0/PBMR
011 PBR1
100
PBR0/PBMR
AB x R{& DBR/DBMR}
101 PBR1
110
PBR1
AB x R{& DBR/DBMR}
111 PBR0/PBMR