Timer/PWM Module (TPM)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
19-12
19.3.5
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any
write to the channel registers is ignored during the input capture mode.
Table 19-6. Mode, Edge, and Level Selection
CPWMS
MSnB:MSnA
ELSnB:ELSnA
Mode
Configuration
X
XX
00
Pin is not controlled by TPM. It is reverted to general purpose I/O or
other peripheral control
0
00
01
Input capture
Capture on rising edge only
10
Capture on falling edge only
11
Capture on rising or falling edge
01
00
Output compare
Software compare only
01
Toggle output on channel match
10
Clear output on channel match
11
Set output on channel match
1X
10
Edge-aligned
PWM
High-true pulses (clear output on channel match)
X1
Low-true pulses (set output on channel match)
1
XX
10
Center-aligned
PWM
High-true pulses (clear output on channel match
when TPM counter is counting up)
X1
Low-true pulses (set output on channel match when
TPM counter is counting up)
7
6
5
4
3
2
1
0
R
TPMxCnV[15:8]
W
Reset
0
0
0
0
0
0
0
0
Figure 19-12. TPM Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
TPMxCnV[7:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 19-13. TPM Channel Value Register Low (TPMxCnVL)
