Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-27
MCF51CN128 Reference Manual, Rev. 6
16.5.2
Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations you must initialize prior to enabling the FEC.
16.5.2.1
Hardware Controlled Initialization
In the FEC, hardware resets registers and control logic that generate interrupts. A hardware reset negates
output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or
software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the
TCR and RCR are not reset, but the entire data path is reset.
16.5.3
User Initialization (Prior to Setting ECR[ETHER_EN])
You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values depend
on the particular application. The sequence is not important.
defines Ethernet MAC registers requiring initialization.
defines FEC FIFO/DMA registers that require initialization.
Table 16-28. ECR[ETHER_EN] De-Assertion Effect on FEC
Register/Machine
Reset Value
XMIT block
Transmission is aborted (bad CRC
appended)
RECV block
Receive activity is aborted
DMA block
All DMA activity is terminated
RDAR
Cleared
TDAR
Cleared
Descriptor Controller block
Halt operation
Table 16-29. User Initialization (Before ECR[ETHER_EN])
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
TFWR (optional)
IALR / IAUR
GAUR / GALR
PALR / PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
RCR
TCR
MSCR (optional)
