Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual,
Rev. 6
8-10
Freescale Semiconductor
8.3.1
Interrupt OR Mask Register (INTC_ORMR)
The INTC_ORMR provides a mechanism to enable/disable the combined interrupt requests associated
with SCI3 and the FEC.
The SCI3 and FEC modules have interrupt sources that are the logical summation (the boolean OR) of
multiple interrupt requests. These two interrupt requests can be configured to enable the OR’d version of
the interrupt request or the separate individual requests.
The reset state of the INTC_ORMR disables (masks) the OR’d interrupt requests. If the OR’d version of
the SCI3 or FEC interrupt sources is used, they first must be properly enabled (unmasked) by writing to
this register.
Table 8-4. CF1_INTC Memory Map
Offset
Address
Register Name
Register Description
Width
(bits)
Access
Reset Value
Section/
Page
0x0C
INTC_ORMR
CF1_INTC OR Mask Register
16
R/W
0x0140
0x10
INTC_FRC
CF1_INTC Force Interrupt Register
8
R/W
0x00
0x18
INTC_PL6P7
CF1_INTC Programmable Level 6, Priority 7
8
R/W
0x00
0x19
INTC_PL6P6
CF1_INTC Programmable Level 6, Priority 6
8
R/W
0x00
0x1B
INTC_WCR
CF1_INTC Wakeup Control Register
8
R/W
0x80
0x1E
INTC_SFRC
CF1_INTC Set Interrupt Force Register
8
Write
—
0x1F
INTC_CFRC
CF1_INTC Clear Interrupt Force Register
8
Write
—
0x20
INTC_SWIACK
CF1_INTC Software Interrupt Acknowledge
8
Read
0x00
0x24
INTC_LVL1IACK
CF1_INTC Level 1 Interrupt Acknowledge
8
Read
0x18
0x28
INTC_LVL2IACK
CF1_INTC Level 2 Interrupt Acknowledge
8
Read
0x18
0x2C
INTC_LVL3IACK
CF1_INTC Level 3 Interrupt Acknowledge
8
Read
0x18
0x30
INTC_LVL4IACK
CF1_INTC Level 4 Interrupt Acknowledge
8
Read
0x18
0x34
INTC_LVL5IACK
CF1_INTC Level 5 Interrupt Acknowledge
8
Read
0x18
0x38
INTC_LVL6IACK
CF1_INTC Level 6 Interrupt Acknowledge
8
Read
0x18
0x3C
INTC_LVL7IACK
CF1_INTC Level 7 Interrupt Acknowledge
8
Read
0x18