Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual,
Rev. 6
8-14
Freescale Semiconductor
Typically, the interrupt mask level loaded into the processor's status register field (SR[I]) during the
execution of the stop instruction matches the INTC_WCR[MASK] value.
The interrupt controller's wait mode wakeup signal is defined as:
wait wakeup = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK])
8.3.5
INTC Set Interrupt Force Register (INTC_SFRC)
The INTC_SFRC register provides a simple memory-mapped mechanism to set a given bit in the
INTC_FRC register to assert a specific level interrupt request. The data value written causes the
appropriate bit in the INTC_FRC register to be set. Attempted reads of this register generate an error
termination.
This register is provided so interrupt service routines can generate a forced interrupt request without the
need to perform a read-modify-write sequence on the INTC_FRC register.
Figure 8-6. INTC_SFRC Register
Offset: CF1_INT 0x1B (INTC_WCR)
Access: Read/Write
7
6
5
4
3
2
1
0
R
ENB
0
0
0
0
MASK
W
Reset
1
0
0
0
0
0
0
0
Figure 8-5. Wakeup Control Register (INTC_WCR)
Table 8-8. INTC_WCR Field Descriptions
Field
Description
7
ENB
Enable wakeup signal.
0 Wakeup signal disabled
1 Enables the assertion of the combinational wakeup signal to the clock generation logic.
6–3
Reserved, must be cleared.
2–0
MASK
Interrupt mask level. Defines the interrupt mask level during wait mode and is enforced by the hardware to be within
the range 0–6. If INTC_WCR[ENB] is set, when an interrupt request of a level higher than MASK occurs, the interrupt
controller asserts the wait mode wakeup signal to the clock generation logic.
Offset: CF1_INT 0x1E (INTC_SFRC)
Access: Write-only
7
6
5
4
3
2
1
0
R
W
SET
Reset
0
0
0
0
0
0
0
0
