ColdFire Core
Freescale Semiconductor
7-5
MCF51CN128 Reference Manual, Rev. 6
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
These instructions are described in the
ColdFire Family Programmer’s Reference Manual
. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
NOTE
The SSP is loaded during reset exception processing with the contents of
location 0x(00)00_0000.
7.2.4
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
BDM: Load: 0x6F (A7)
Store: 0x4F (A7)
Load: 0xE0 (OTHER_A7)
Store: 0xC0 (OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 7-4. Stack Pointer Registers (A7 and OTHER_A7)
BDM: LSB of Status Register (SR)
Load: 0xEE (SR)
Store: 0xCE (SR)
Access: User read/write
BDM read/write
7
6
5
4
3
2
1
0
R
0
0
0
X
N
Z
V
C
W
Reset:
0
0
0
—
—
—
—
—
Figure 7-5. Condition Code Register (CCR)
Table 7-2. CCR Field Descriptions
Field
Description
7–5
Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
