Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-2
Freescale Semiconductor
5.3.1
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
If the COP watchdog is not used in an application, it can be disabled by clearing SOPT1[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the
selected time-out period. Writes do not affect the data in the read-only SRS. When the write sequence is
complete, the COP time-out period is restarted. If the program fails to do this during the time-out period,
the microcontroller resets. See
Section 5.7.2, “System Reset Status Register (SRS)
,” for additional
information.
The SOPT2[COPCLKS] field (see
Section 5.7.4, “System Options 2 Register (SOPT2),”
for additional
information) selects the clock source used for the COP timer. The clock source options are the bus clock
or an internal 1 kHz clock source. With each clock source, there are three associated time-outs controlled
by SOPT1[COPT].
summarizes the control functions of the COPCLKS and COPT bits. The COP
watchdog defaults to operation from the 1 kHz clock source and the longest time-out (2
10
cycles).
When the bus clock source is selected, windowed COP operation is available by setting SOPT1[COPW].
In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected
time-out period. A premature write immediately resets the microcontroller. When the 1 kHz clock source
is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers and after any system
reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. This prevents accidental
changes if the application program gets lost.
If the bus clock source is selected, the COP counter does not increment while the microcontroller is in
background debug mode or while the system is in stop mode. The COP counter resumes when the
microcontroller exits background debug mode or stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero after entry to either
background debug mode or stop mode and begins from zero after exit from background debug mode or
stop mode.
5.3.2
Illegal Opcode Detect (ILOP)
By default the V1 ColdFire core enables the generation of an MCU reset in response to the processor's
attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal line
F instruction or the detection of a privilege violation (attempted execution of a supervisor instruction while
in user mode).
The attempted execution of the STOP instruction with (SOPT[STOPE] and SOPT[WAITE] cleared) is
treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM] cleared is treated as an illegal
instruction.
