Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-12
Freescale Semiconductor
5.7.2
System Reset Status Register (SRS)
This register includes read-only status flags to indicate the source of the most recent reset. When a debug
host forces reset by setting CSR2[BDFR], none of the status bits in SRS are set. Writing any value to this
register address clears the COP watchdog timer without affecting the contents of this register. The reset
state of these bits depends on what caused the microcontroller to reset.
Table 5-4. IRQSC Register Field Descriptions
Field
Description
7
Reserved, must be cleared.
6
IRQPDD
Interrupt Request (IRQ) Pull Device Disable
— This read/write control bit disables the internal
pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device is enabled if IRQPE = 1.
1 IRQ pull device is disabled if IRQPE = 1.
This bit overrides the pull-up enable logic in the GPIO controls when IRQ is assigned this pin.
5
IRQEDG
Interrupt Request (IRQ) Edge Select
— This read/write control bit selects the polarity of edges or levels on the
IRQ pin that causes IRQF to set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both
edges and levels or only edges. When IRQEDG is set and the internal pull device is enabled, the pull-up device
is reconfigured as an optional pull-down device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable
— This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can
be used as an external interrupt request. Note that the IRQ pin function must also be enabled via the MC
1
registers.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
1
MC = Port Mux Control
3
IRQF
IRQ Flag
— This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
2
IRQACK
IRQ Acknowledge
— This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable
— This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF is set.
0
IRQMOD
IRQ Detection Mode
— This read/write control bit selects edge-only detection or edge-and-level detection. The
IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See
Section 5.4.2.2, “Edge and Level Sensitivity
,” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
