NXP Semiconductors freescale MPC5668E, User Manual, Page: 24 / 54

MPC5668EVB Users Manual Rev 0.1 May 2009
MPC5668EVBUM/D Page 20 of 29
The Ethernet circuitry is
located in the right edge of
the EVB in an area titled
“Ethernet”
3.9 Ethernet
The EVB is fitted with a National Semiconductor DP8348C Ethernet physical interface (U9) and a Pulse Jack
J1011F21PNL RJ45 connector with integrated activity LED’s and magnetics (J63).
The National Semiconductor DP8348C physical interface is connected to the MII on the MPC5668. This is a
fixed connection with no means of isolation. Pullups are also also present on some of these signals. These
are detailed in the table below. Please be aware of this when using I/O on ports G and H.
Table 3-20 Pull up/ Pull down resistors on Ports G and H for Ethernet Physical
Port Pin Pull Direction Strength
PG[9] Down (GND) 2.2k Ω
PG[7] Up (3.3v SR) 1.5k Ω
PG[12] Down (GND) 2.2k Ω
PG[13] Down (GND) 2.2k Ω
PG[14] Down (GND) 2.2k Ω
PG[15] Down (GND) 2.2k Ω
PH[1] Down (GND) 2.2k Ω
PH[2] Down (GND) 2.2k Ω
PH[3] Down (GND) 2.2k Ω
PH[4] Down (GND) 2.2k Ω
PH[5] Down (GND) 2.2k Ω
PH[6]
Down (GND) 2.2k Ω
PH[7]
Down (GND) 2.2k Ω
The VDDE3 voltage domain that is used by ports G and H should be set to 3.3v (J44 Pos 2-3) when power is
applied to the physical interface.
Power can be removed from the physical interface via J62.
Table 3-21 Ehternet Physical Interface Power Supply Enabled (J26)
Jumper Position PCB
Legend
Description
J62
(PHY PWR)
FITTED (D)
PHY PWR
The DP4348C Ethernet Physical Interface is powered
from the 3.3v SR.
REMOVED
The DP4348C Ethernet Physical Interface is not
powered