NXP Semiconductors freescale MPC5668E User Manual Download Page 15

MPC5668EVB Users Manual Rev 0.1

 

 

        

  May 2009 

MPC5668EVBUM/D  

                               Page 11 of 29 

 

The

 RESET switch (RED) 

and LVI circuitry is located 
to the t left of the MCU in 
the area titled “RESET “

 

 

 
 

3.3  Reset Control (Jumper J75) 

 

 
 
The EVB incorporates an LVI (Low Voltage Inhibit) device to provide under-voltage protection for the two main 
switching regulators (5v and 3.3v).  When either of these regulator voltages drops below a certain threshold 
level, the LVI will assert the MCU reset line to prevent incorrect operation of the MCU (or EVB circuitry).  
 
The table below shows the approximate threshold voltages for each regulator 
 

Table 3-7   LVI Monitor Threshold Voltages 

Regulator 

Minimum Voltage Before MCU 

reset 

5.0V Switcher 

1.47V 

3.3V Switcher 

1.47V 

 
The LVI is powered from the 5.0V switching regulator and monitors the 3.3V regulator using a 2

nd

 power fail 

monitor circuit. The LVI also provides a de-bounced input for EVB reset switch SW5.  
 
Jumpers are provided to disable either the main LVI reset out (which affects the reset from the 5.0V switching 
regulator and from the reset switch) or the power fail out circuit (which only affects the reset from the 3.3V 
regulator). If the 5v regulator LVI is disabled, the reset switch will not function.  
 

Table 3-8   LVI Control Jumpers 

Jumper  

Position 

PCB Legend  Description 

J75 

Posn 1-2

 

FITTED 

(D)

 

 

5.0V switching regulator is monitored, Reset switch 
active     

REMOVED

 

 

5.0V switching regulator is not monitored, Reset 
switch inactive     

J75 

Posn 3-4

 

FITTED 

(D)

 

 

3.3V switching regulator is monitored 

REMOVED

 

 

3.3V switching regulator is not monitored 

 
 

Notes: 

-

 

If the 5.0V switching regulator is disabled for any reason, the LVI circuit will attempt to assert the MCU 
Reset signal. Jumper shunts on jumper J20 position 1-2 and 3-4 must be removed in this situation. 
This will also leave the reset switch SW5 inoperative. 

-

 

If the 3.3V regulator is disabled, the shunt on jumper J20 position 3-4 must be removed to prevent the 
LVI asserting reset.  

 

3.3.1  Reset LEDs 

 
There are two reset LED’s, DS2 (AMBER) and DS3 (RED), placed adjacent to the EVB RESET switch to 
indicate the RESET status of the EVB and MCU.  
 
LED DS3, titled “

RST

”, will illuminate if the MCU itself issues a reset. In this condition, LED DS2 will not 

illuminate. 
 
LED DS2, titled “

USR

”, will illuminate when one of the following external hardware devices issues a reset to 

the MCU:  

-

 

LVI circuitry (either an under-voltage detection or the reset switch is being pressed) 

-

 

There is a reset being asserted from the user connectors or from the daughter card 

-

 

There is a reset being driven from the Nexus or JTAG debug probe 

 

Note that LED DS3 (MCU Reset) will also illuminate during an external (user) reset!

 

 

 

Summary of Contents for freescale MPC5668E

Page 1: ...MPC5668EVB Users Manual Revision 0 1 May 2009...

Page 2: ...rating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the...

Page 3: ...3 4 ONCE AND NEXUS CONFIGURATION J32 J70 13 3 4 1 Debug Connector Pinouts 14 3 5 CAN CONFIGURATION J20 J21 J29 J30 J31 15 3 6 RS232 CONFIGURATION J6 J17 J18 J23 J24 16 3 7 LIN CONFIGURATION J3 J4 J5 J...

Page 4: ...13 TABLE 3 11 JTAG NEXUS TARGET RESET ROUTING 13 TABLE 3 12 ONCE NEXUS TCLK TERMINATION CONTROL 13 TABLE 3 13 NEXUS DEBUG CONNECTOR PINOUT 14 TABLE 3 14 CAN CONTROL JUMPERS J30 J31 J7 15 TABLE 3 15 RS...

Page 5: ...668 family of microprocessors and to facilitate hardware and software development At the time of writing this document the MPC5668 family is offered in a 208MAPBGA package A 256MAPBGA package supporti...

Page 6: ...male connector PC RS 232 compliant via a Maxim physical interface SCI channels C and D can be routed to LIN interface header 0 1 and molex connectors both will full physical transceivers FlexCAN chann...

Page 7: ...way jumpers have been aligned such that Pin 1 is either to the top or to the left of the jumper On 2 way jumpers the source of the signal is connected to Pin 1 The EVB has been designed with ease of u...

Page 8: ...s connector should be used to connect the supplied wall plug mains adapter Note if a replacement or alternative adapter is used care must be taken to ensure the 2 1mm plug uses the correct polarisatio...

Page 9: ...Enabled J83 5 0V FITTED DISABLE 5 0V switching regulator output is Disabled REMOVED D 5 0V switching regulator output is Enabled J84 5 0V LINEAR FITTED D ENABLE 5 0V linear regulator output is Enable...

Page 10: ...CU regulators to be disabled by changing VRCSEL to EXT and applying external voltages to the VDDSYN and VDD33 inputs When in 3 3v mode VDDSYN and VDD33 inputs must always be supplied externally The VD...

Page 11: ...D D MCU VDD33 pin is not powered externally J50 VDDSYN FITTED MCU VDDSYN pin is powered from switching regulator REMOVED D MCU VDDSYN pin is not powered externally 3 3v 2 5V J45 VDDEMLB 1 2 D 2 5V MCU...

Page 12: ...while considering if any of the EVB components or peripherals you require will be affected Table 3 4 details a list of the various EVB components and peripherals powered by the regulators Table 3 4 Po...

Page 13: ...B Clock Selection Table 3 5 Clock Source Jumper Selection Jumper Position PCB Legend Description J85 U20 PWR FITTED D EVB oscillator module U20 is powered REMOVED EVB oscillator module U20 is not powe...

Page 14: ...using the 32KHz crystal PA 14 and PA 15 will not be visible on P17 Port A header Figure 3 6 EVB Clock Selection Table 3 6 32Khz Crystal Jumper Selection Jumper Position PCB Legend Description J67 Mus...

Page 15: ...Table 3 8 LVI Control Jumpers Jumper Position PCB Legend Description J75 Posn 1 2 FITTED D 5 0V switching regulator is monitored Reset switch active REMOVED 5 0V switching regulator is not monitored R...

Page 16: ...of an AND gate and then converted to an open drain output which is directly connected to the MCU reset pin Reset Out The MCU reset pin is buffered to provide a reset out signal capable of driving the...

Page 17: ...w Some debug probes have the ability to assert and also monitor the state of the MCU reset line This is not possible when the reset signal is buffered so a jumper J32 is included to allow routing the...

Page 18: ...ction Pin No Function Connection 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 MDO 9 MCU M5 6 CLKOUT MCU PK9 7 Vendor I O 2 TP25 8 MDO 8 MCU L5 9 Reset In Reset CCT 10 EVTI MCU M11 11 TDO MCU M3 12 VR...

Page 19: ...J7 Jumper Position PCB Legend Description J30 Posn 1 2 FITTED D 5v is applied to both CAN transceivers VCC REMOVED No 5v power is applied to CAN transceivers J30 Posn 3 4 FITTED D 12v Power is applie...

Page 20: ...ace as described below There is also a global power jumper J9 controlling the power to the RS232 transceiver Table 3 15 RS232 Control Jumpers Jumper Position PCB Legend Description J6 SCI PWR FITTED D...

Page 21: ...e mode as defined in the table below Table 3 16 LIN Control Jumpers Jumper Position PCB Legend Description J5 LIN C M FITTED D LIN C transceiver is configured for LIN Master mode REMOVED LIN C transce...

Page 22: ...FITTED D TXEN MCU PK8 is connected to Flexray B transceiver TXEN REMOVED MCU PK8 is not connected to Flexray B transceiver TXEN J27 Flex B Posn 5 6 FITTED D RX MCU PK6 is connected to Flexray B trans...

Page 23: ...xray B interface BGE signal is pulled to VIO REMOVED Flexray B interface BGE signal is unterminated J28 Flex B Posn 3 4 FITTED D EN Flexray B interface EN signal is pulled to VIO REMOVED Flexray B int...

Page 24: ...ports G and H Table 3 20 Pull up Pull down resistors on Ports G and H for Ethernet Physical Port Pin Pull Direction Strength PG 9 Down GND 2 2k PG 7 Up 3 3v SR 1 5k PG 12 Down GND 2 2k PG 13 Down GND...

Page 25: ...supplies domains referred to in this table are for the Flash based INIC Please refer to the schematics to see how this affects the supply domains of the ROM INIC if it has been fitted Table 3 22 INIC...

Page 26: ...to the EVB INIC 2 3 INIC150 PSO is Routed to the MOST150 header J39 MLBDAT 1 2 D EVB MLBDAT is Routed to the EVB INIC 2 3 INIC150 MLBDAT is Routed to the MOST150 header J40 SDA 1 2 D EVB SDA is Routed...

Page 27: ...detailed in table x below Table 3 24 Phantom Port Control J35 J36 J55 Jumper Position PCB Legend Description J76 FITTED D CLK PF0 DSPI A CLK is connected to the phantom port circuitry REMOVED PF0 DSPI...

Page 28: ...tions for example the Nexus and External bus as shown by the shaded boxes in the table below Table 4 1 EVB MCU Pin Usage Function Port A Port B Port C Port D Port E Port F Port G Port H Port J Port k...

Page 29: ...ED LIN C RX LIN C RX from MCU Connected to LIN Interface J16 LIN C FITTED LIN C EN LIN D Bus Enable Physical Interface J17 SCI A FITTED SCI A RX MCU RXD A is routed to MAX3223 J18 SCI A FITTED SCI A T...

Page 30: ...1 2 FITTED VCC 5v is applied to both CAN transceivers VCC J30 CAN Posn 3 4 FITTED VIO Power is applied to both CAN transceivers VIO J31 CAN A Posn 1 2 FITTED TX MCU CNTX A is connected to CAN control...

Page 31: ...J69 BOOT CFG 1 2 FLASH MCU boots from internal flash J70 TCLK PULL 1 2 VDDE2 JTAG NEXUS TCLK signal is pulled to VDDE2 via 10K J71 32KHz CLK 1 2 Y3 32Khz Crystal Y2 is connected to MCU J72 Not Implem...

Page 32: ...he EVB core voltages to be monitors by the ATD J74 allows the 2 5v 3 3v and 5v Switcher and Linear regulator outputs to be connected to the ATD inputs J73 allows the 12v EVB supply to be monitored via...

Page 33: ...ort C Connector Pinout P19 Pin Function Pin Function GPIO 1st Alt GPIO 1st Alt 1 PC0 AN32 2 PC1 AN33 3 PC2 AN34 4 PC3 AN35 5 PC4 AN36 6 PC5 AN37 7 PC6 AN38 8 PC7 AN39 9 PC8 AN40 10 PC9 AN41 11 PC10 AN...

Page 34: ...10 SIN_C 12 PF11 PCS_C 0 13 PF12 SCK_D 14 PF13 SOUT_D 15 PF14 SIN_D 16 PF15 PCS_D 0 17 GND 18 GND 6 1 7 Port G DSPI eMIOS FEC P27 Table 6 8 Port F Connector Pinout P27 Pin Function Pin Function GPIO 1...

Page 35: ...9 8 PJ7 eMIOS 8 9 PJ8 eMIOS 7 10 PJ9 eMIOS 6 11 PJ10 eMIOS 5 12 PJ11 eMIOS 4 13 PJ12 eMIOS 3 14 PJ13 eMIOS 2 15 PJ14 eMIOS 1 16 PJ15 eMIOS 0 17 GND 18 GND 6 1 10 Port K RESET MLB Connector P30 Table 6...

Page 36: ...prototyping area are connected to the CAN C F pins of the MCU as well as power and the DB9 connectors This allows an additional 4 CAN physical interfaces to be added to the EVB for evaluation with the...

Page 37: ...MPC5668EVB Users Manual Rev 0 1 May 2009 MPC5568EVBUM D Page A 1 Appendix A EVB Schematics...

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