FRDM-KL43Z User’s Guide, Rev. 1
10
NXP Semiconductors
FRDM-KL43Z hardware description
range) and 8–32 MHz (high frequency mode, high range). The KL43Z256 on the FRDM-KL43Z can be
clocked from 32 kHz external crystal.
5.3.2
USB interface
The Kinetis KL43 microcontrollers feature full speed device USB controller (with crystal-less feature).
The USB interface on the FRDM-KL43Z is configured as a full-speed USB device. VREGIN must be
powered to enable the internal circuitry of USB (by jumper J7).
5.3.3
Serial port
The primary serial port interface signals are PTA1 LPUART0 RX and PTA2 LPUART0 TX. These signals
are connected via the OpenSDA.
5.3.4
Reset
The RESET signal on the K20 is connected externally to a push button, SW2, and also to the OpenSDA
circuit. The reset button can be used to force an external reset event in the target MCU. The reset button
can also be used to force the OpenSDA circuit into bootloader mode. Please refer to
, for more details.
5.3.5
Debug
The sole debug interface on all Kinetis L series devices is a Serial Wire Debug (SWD) port. The primary
controller of this interface on the FRDM-KL43Z is the onboard OpenSDA circuit (see
). However, an unpopulated 10-pin (0.05”) Cortex Debug connector, J11,
provides access to the SWD signals. The Samtec FTSH-105-02-F-D or compatible connectors can be
added to the J11 through-hole debug connector to allow for an external debug cable to be connected.
5.3.6
Segment LCD
FRDM-KL43Z uses a 4–digit display (LUMEX LCD-S401M16KR) 4
8 segments. The following table shows
connection from KL43 to s401 display.
Table 4. sLCD connections
s401 pin
KL43 LCD Pin
1
LCD_P59 (COM0)
2
LCD_P60 (COM1)
3
LCD_P14 (COM2)
4
LCD_P15 (COM3)
5
LCD_P20 (1D/1E/1G/1F)
6
LCD_P24 (DP1/1C/1B/1A)
7
LCD_P26 (2D/2E/2G/2F)
