NXP Semiconductors EVB912UF32, User Manual, Page: 34 / 44

EVB912UF32 Evaluation Board- Rev 1 User’s Manual
28 Support Information MOTOROLA
Support Information
Figure 3-10 J4 Breakout Header Pin Assignments
Table 3-9 J4 Breakout Header Signal Descriptions
J4
GND 1
• •
2 VDD
VRGEN 3
• •
4 REF3V
CF_CD 5
• •
6 XIRQ_B
BVD1_DASP 7
• •
8 IRQ_B
R_W 9
• •
10 VS1
LSTRB 11
• •
12 ECLK
XCLKS 13
• •
14 PWROFF3V
PWROFF5V 15
• •
16 RESET_B
MODA 17
• •
18 MODB
BKGD 19
• •
20 P5V
Pin(s) Signal Description
1 GND GROUND
2 VDD USB Power
3 VRGEN GROUND
4 REF3V 3 Volt Reference
5 CF_CD Clock
6 XIRQ_B Fast Interrupt Request to processor
7 BVD1_DASP Device Active or Slave Present — Bidirectional
8 IRQ_B Interrupt Request to processor
9 R_W Read/Write
10 VS1 VOLTAGE SENSE 1 — Output from CF cards
11 LSTRB Low Byte Strobe — Output from processor
12 ECLK Internal Bus Clock
13 XCLKS Function was removed, Port E, pin 7
14 PWROFF3V Power OFF 3 volts — Controls VDDX
15 PWROFF5V Power OFF 5 volts — Controls VDDX
16 RESET_B Reset — Active Low
17 MODA Mode Bit A — Power up configuration bit
18 MODB Mode Bit B — Power up configuration bit
19 BKGD Background debug pin, shared with MODC
20 P5V +5 volt power