D[7]
R
4
First Byte
R
0
G
5
G
3
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[7]
G
2
Second Byte
B
4
B
0
D[6]
D[5]
G
0
D[4]
D[3]
D[2]
D[1]
D[0]
PCLK
HREF
D[7:0]
Last
Byte
Last
Byte
First
Byte
(Row Data)
t
PCLK
t
PHL
t
PHL
t
HD
t
SU
t
PDV
Figure 1. Camera module configuration
2. The resolution should be configured as QVGA (320 × 240).
6 Pin description
6.1 Connection of interface
Camera
D0
D1
D2
D3
D4
D5
D6
D7
SIOC
SIOD
VSYNC
HREF
PCLK
XCLK
VCC
GND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.20
P1.21
P0.13
P0.14
P0.15
P0.16
Power
I2C port
Parallel data port
control signals
VCC
GND
LPC5500
Figure 2. Connection of interface
NXP Semiconductors
Pin description
Camera Interface in LPC55(S)xx, Rev. 3, 07 September 2021
Application Note
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