DSP56858EVM User Manual, Rev. 3
2-4
Freescale Semiconductor
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K
u
16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2
. Using CS1 and CS2, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable program memory, data memory, or both. Additionally, CS1 and CS2 can be
configured to assign this memory’s size and starting address to any modulo address space.
This memory bank will operate with one wait state access while the 56858 is running at 120MHz
and can be disabled by removing the jumpers at JG2.
56858
GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
JG2
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
CS1
CS2
1
3
2
4
LB
HB
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
Summary of Contents for 56858
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