NXP Semiconductors 56858 Page 1 User Manual Download

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56F850
16-bit Digital Signal Controllers

freescale.com

56858

Evaluation Module User Manual

DSP56858EVMUM
Rev. 3
07/2005

Summary of Contents for 56858

Page 1: ...56F850 16 bit Digital Signal Controllers freescale com 56858 Evaluation Module User Manual DSP56858EVMUM Rev 3 07 2005 ...

Page 2: ......

Page 3: ...5 2 4 RS 232 Serial Communications 2 6 2 5 Clock Source 2 7 2 6 Operating Mode 2 8 2 7 Debug LEDs 2 8 2 8 Debug Support 2 9 2 8 1 JTAG Connector 2 10 2 8 2 Parallel JTAG Interface Connector 2 11 2 9 External Interrupts 2 13 2 10 Reset 2 14 2 11 Power Supply 2 15 2 12 Stereo Codec 2 16 2 12 1 Analog Input Output 2 17 2 12 2 Digital Interface 2 17 2 13 Daughter Card Connectors 2 19 2 13 1 Memory Dau...

Page 4: ...DSP56858EVM User Manual Rev 3 ii Freescale Semiconductor Appendix A 56858EVM Schematics Appendix B 56858EVM Bill of Material ...

Page 5: ...3 SPI EEPROM Memory Block Diagram 2 5 2 4 Schematic Diagram of the RS 232 Interface 2 6 2 5 Schematic Diagram of the Clock Interface 2 7 2 6 Schematic Diagram of the Debug LED Interface 2 9 2 7 Block Diagram of the Parallel JTAG Interface 2 11 2 8 Schematic Diagram of the User Interrupt Interface 2 13 2 9 Schematic Diagram of the RESET Interface 2 14 2 10 Schematic Diagram of the Power Supply 2 15...

Page 6: ...DSP56858EVM User Manual Rev 3 iv Freescale Semiconductor ...

Page 7: ...rol 2 8 2 5 JTAG Connector Description 2 10 2 6 Parallel JTAG Interface Disable Jumper Selection 2 10 2 7 Parallel JTAG Interface Connector Description 2 12 2 8 Codec Sample Rate Selector 2 16 2 9 ESSI Port Connector Description 2 18 2 10 GPIO Port Connector Description 2 19 2 11 Memory Daughter Card Connector Description 2 19 2 12 Peripheral Daughter Card Connector Description 2 21 2 13 Host Inte...

Page 8: ...DSP56858EVM User Manual Rev 3 vi Freescale Semiconductor ...

Page 9: ...n This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56858 hardware Appendix A 56858EVM Schematics contains the schematics of the 56858EVM Appendix B 56858EVM Bill of Material provides a list of the materials used on the 56858EVM board Suggested Reading More docume...

Page 10: ...ext and in most figures WE OE In schematic drawings Active Low Signals may be noted by a backslash WE Hexadecimal Values Begin with a sym bol 0FF0 80 Decimal Values No special symbol attached to the number 10 34 Binary Values Begin with the letter b attached to the number b1010 b0011 Numbers Considered positive unless specifically noted as a negative value 5 10 Voltage is often shown as positive 3...

Page 11: ...atform which allows a customer to evaluate the silicon and develop his application GPIO General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input HI Host Interface a communications port on Freescale s family of controllers IC Integrated C...

Page 12: ...essor User s Manual DSP5685xUM Frees cale Semiconductor 3 DSP56858 16 Bit Digital Signal Processor Technical Data DSP56858 Freescale Semiconductor SPI Serial Peripheral Interface a communications port on Freescale s family of controllers SRAM Static Random Access Memory SSI Synchronous Serial Interface a communications port on Freescale s family of controllers THD Total Harmonic Distortion USB Uni...

Page 13: ...a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the b...

Page 14: ... to fully exploit the 56858 s features to optimize the performance of his product as shown in Figure 1 1 56858 RESET MODE Address Data Control JTAG EOnCE XTAL EXTAL SPI SCI0 ESSI0 GPIO 1 8V 3 3V GND Peripheral Daughter Card Connector RESET LOGIC MODE LOGIC CS0 Program Memory 128Kx16 bit SRAM Memory Daughter Card Connector JTAG Connector Parallel JTAG Interface 4 00MHz Crystal DSub 25 Pin CS1 CS2 D...

Page 15: ...2 3 4 1 2 9 10 JG6 JG6 JG1 J4 J5 JG1 Figure 1 2 56858EVM Jumper Reference Table 1 1 56858EVM Default Jumper Options Jumper Group Comment Jumpers Connections JG1 Enable on board Word selectable SRAM via CS0 U2 1 2 JG2 Enable on board Byte selectable SRAM via CS1 CS2 U3 1 2 3 4 JG3 Use on board EXTAL crystal input for oscillator 2 3 JG4 Use on board XTAL crystal input for oscillator 1 2 JG5 Enable o...

Page 16: ...he parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56858EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12 0V DC 1 2A switching power supply or the external 5 0V DC 1A lab power supply is not plugged into a 120V AC powe...

Page 17: ...g the architecture and instruction set of the 56858 processor The main features of the 56858EVM with board and schematic reference designators include 56858 16 bit 1 8V 3 3V Digital Signal Processor operating at 120MHz U1 External fast static RAM FSRAM memory configured as 128Ku16 bit of memory U2 with one wait state at 120MHz via CS0 128Ku16 bit of memory U3 with one wait state at 120MHz via CS1 ...

Page 18: ...ses a Freescale DSP56858FV120 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 120MHz A full description of the 56858 including functionality and user information is provided in these documents DSP56858 Technical Data DSP56858 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and...

Page 19: ...see the FSRAM schematic diagram in Figure 2 1 CS0 can be configured to use this memory bank as 16 bit program memory data memory or both Additionally CS0 can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with one wait state access while the 56858 is running at 120MHz and can be disabled by removing the jumper at JG1 56858 ...

Page 20: ... accessable program memory data memory or both Additionally CS1 and CS2 can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with one wait state access while the 56858 is running at 120MHz and can be disabled by removing the jumpers at JG2 56858 GS72116 A0 A16 D0 D15 RD WR A0 A16 DQ0 DQ15 OE WE CE JG2 Jumper Pin 1 2 Enable SR...

Page 21: ...a into the 56858 s internal or external memory spaces Jumper block JG10 is provided to allow the user to disconnect the on board SPI EEPROM Data FLASH from the SPI port and allow him to connect his own SPI port peripheral The header details are shown in Table 2 1 56858 MOSI SRFS MISO SRCK SCLK STCK SS STFS PC3 Serial EEPROM Data FLASH SDI SDO SCK CS Data FLASH Enable SPI Port Connector JG10 Figure...

Page 22: ... P3 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P3 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG9 56858 RS 232 Level Converter Interface TXD0 RXD0 R1in T1out T1in R1out FORCEOFF JG9 1 2 6 3 2 7 8 4 5 x 1 9 3 3V Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 P3 Figu...

Page 23: ... JG4 see Figure 2 5 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2 The input frequency would then be injected on JG3 s pin 2 If the controller needs to be synchronized to the codec s sample frequency then the controller s input frequency should be jumpered using the 12 2280MHz codec frequency If the input frequency...

Page 24: ... from External byte wide memory 1 3 4 5 6 Bootstrap from SPI 2 1 2 5 6 Normal Expanded mode 3 5 6 Development Expanded mode 4 1 2 3 4 Host Interface Port Single Strobe mode 5 3 4 Host Interface Port Dual Strobe mode 2 7 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution wit...

Page 25: ... LED YELLOW LED RED LED PD3 PD4 PD5 Figure 2 6 Schematic Diagram of the Debug LED Interface 2 8 Debug Support The 56858EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host...

Page 26: ...a debugger program Table 2 5 shows the pin out for this connector Table 2 5 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 DE 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG5 Reference Table 2 6 for this...

Page 27: ...ad programs and work with the 56858 s registers Table 2 7 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG5 should be removed as shown in Table 2 6 DB 25 Connector Parallel JTAG Interface 56858 TDI TDO P_TRST TMS TCK P_RESET OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN EN TDI TDO TRST TMS TCK RESET JG5 1 2 3 3V Jumper Removed Enable JTAG I F Jumper Pin 1 2 ...

Page 28: ...1 NC 14 NC 2 PORT_RESET 15 PORT_IDENT 3 PORT_TMS 16 NC 4 PORT_TCK 17 NC 5 PORT_TDI 18 GND 6 PORT_TRST 19 GND 7 PORT_DE 20 GND 8 PORT_IDENT 21 GND 9 PORT_VCC 22 GND 10 NC 23 GND 11 PORT_TDO 24 GND 12 NC 25 GND 13 PORT_CONNECT DSP56858EVM User Manual Rev 3 2 12 Freescale Semiconductor ...

Page 29: ...tion as shown in Figure 2 8 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 56858 IRQA IRQB 3 3V 3 3V 10K 10K S2 S3 0 1µF 0 1µF Figure 2 8 Schematic Diagram of the User Interrupt Interface ...

Page 30: ...e an internal Power On RESET The 56858EVM provides reset logic to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 9 RESET PUSHBUTTON MANUAL RESET JTAG_TAP_RESET JTAG_RESET RESET TRST Figure 2 9 Schematic Diagram of the RESET Interface ...

Page 31: ...he power regulation on the 56858EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additonal voltage regulation logic on the EVM The additonal voltage regulation logic provides 1 8V DC voltage regulation for the controller s core and 3 3V DC voltage regulation for the controller s I O memory parallel JTAG interface and supporting logic refer to Figure 2 10 Power app...

Page 32: ... 8 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on board codec from the ESSI port and allow him to connect his own codec to the ESSI port see Figure 2 12 The on board codec has analog signal conditioning logic allowing direct connection to its li...

Page 33: ...sts of independent transmitter and receiver sections and is used for serial communication with the codec On the controller side the Serial Transmit Data pin STD0 is an output when data is being transmitted to the codec The Serial Receive Data pin SRD0 is an input when data is being received from the codec These two pins are connected to the codec s Serial Data Input SDIN and Serial Data Output SDO...

Page 34: ...frame i e 16 bits Left channel and 16 bits Right channel The sample rate is selected on the Sample Rate Selector switch S5 see Table 2 8 for selection options Codec control information is sent over a separate serial port using PC3 as the Control Chip Select signal CCS PE2 as the Control Data Input signal CDIN and PE3 as the Control Clock signal CCLK CODEC Enable Logic 56858 CS4218 SDIN SDOUT SCLK ...

Page 35: ...ins the controller s external memory bus signals The other connector J2 contains the controller s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector The controller s external memory bus signals are connected to the Memory Daughter Card Expansion connector J1 Table 2 11 shows the port signal to pin assignments Table 2 11 Memory Daughter Card Connector Description J1 Pin Signal ...

Page 36: ...10 23 D4 24 D11 25 D5 26 D12 27 D6 28 D13 29 A18 30 A17 31 D7 32 D14 33 CS0 34 D15 35 A0 36 RD 37 A1 38 A6 39 A16 40 GND 41 A2 42 A5 43 A3 44 A4 45 CS3 46 CS2 47 3 3V 48 3 3V 49 GND 50 GND 51 5 0V Table 2 11 Memory Daughter Card Connector Description Continued J1 Pin Signal Pin Signal ...

Page 37: ...12 Peripheral Daughter Card Connector Description J2 Pin Signal Pin Signal 1 CS0 PA0 2 CS1 PA1 3 CLKO 4 CS2 PA2 5 TIO0 PG0 6 TIO1 PG1 7 CS3 PA3 8 RSTOUT 9 TIO2 PG2 10 TIO3 PG3 11 NC 12 NC 13 GND 14 GND 15 SRD0 PC1 16 SRD1 PD1 17 SC01 PC4 18 SC11 PD4 19 SCK PF2 20 SCK1 PD2 21 GND 22 GND 23 MOSI PF1 24 SC10 PD3 25 MISO PF0 26 SC12 PD5 27 GND 28 GND 29 SS PF3 30 STD1 PD0 31 SC00 PC3 32 MODA PH0 33 SC...

Page 38: ...des a USB Tranceiver Serial Interface Engine USB Protocol Controller Endpoint FIFOs Local Bus Interface and Configuration Registers Refer to the USB diagram in Figure 2 13 The USB Interface s use of CS3 can be disabled by removing the jumper at JG11 56858 USB Interface D0 D15 A0 A4 DP DM IOR IOW CS JG11 1 Jumper Pin 1 2 Enable USB Jumper Removed Disable USB RD CS3 WR 2 LD0 LD15 LA0 LA4 IRQA IRQ 2 ...

Page 39: ...3 Host Interface Connector Description J4 Pin Signal Pin Signal 1 HD0 2 HD1 3 HD2 4 HD3 5 HD4 6 HD5 7 HD6 8 HD7 9 HA0 10 HA1 11 HA2 12 HRW 13 HDS 14 HCS 15 HREQ 16 HACK 17 3 3V 18 GND 19 3 3V 20 GND 2 16 Test Points The 56858EVM board has a total of seven test points Three digital GND test points are located in corners of the board The 5 0VA and AGND test points are located in the analog corner of...

Page 40: ...DSP56858EVM User Manual Rev 3 2 24 Freescale Semiconductor ...

Page 41: ...56858EVM Schematics Rev 3 Freescale Semiconductor Appendix A 1 Appendix A 56858EVM Schematics ...

Page 42: ... 8 5 8 6 1 7 1 8 1 9 5 8 5 7 6 0 5 6 5 9 5 5 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 2 7 2 8 3 7 2 2 2 3 1 2 3 4 7 4 7 3 1 0 8 1 0 7 9 0 9 1 9 2 3 3 3 4 3 5 4 0 4 1 4 2 4 3 4 4 1 1 9 1 1 8 1 1 7 1 1 6 9 3 3 9 3 8 1 4 5 2 8 7 1 2 5 5 2 0 6 1 4 5 6 8 1 0 5 8 0 1 1 3 1 3 9 1 2 9 2 4 1 6 5 4 8 9 1 2 7 7 2 1 4 7 7 0 1 0 6 1 3 0 6 2 8 2 1 1 5 1 4 1 2 6 TIO0 PG0 TIO1 PG1 TIO...

Page 43: ...13 5090 FAX 480 413 2510 Vcc 2 P O R M O D A M O D B M O D C Vcc 2 P O R IRQA IRQB EXTAL XTAL 1 2 2 8 8 M H Z M O D A M O D B M O D C 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V J G 3 1 2 3 Y 1 4 00MHz R 6 7 1 0 K R 6 6 1 0 K U 2 0 D S 1 8 1 8 2 1 3 V c c R S T G N D C 2 3 0 1uF C 2 4 0 1uF C 2 5 0 1uF J G 4 1 2 3 R 6 8 1 0 K D N P R 6 9 4 7 0 K R 7 0 4 7 0 K R 7 4 4 7 0 K S 4 6 4 2 5 3 1 R 7 3 1 0 K R 7 2 1 0 ...

Page 44: ... D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 1 0 D 1 1 D 1 2 D 1 3 D 1 4 D 1 5 CS0 CS2 CS1 3 3V 3 3V 3 3V 3 3V U 2 G S 7 2 1 1 6 A T P 7 7 8 1 9 10 2 13 14 3 15 16 4 29 30 5 31 32 18 35 36 19 37 38 20 21 24 25 26 27 42 43 44 40 39 41 17 6 22 34 12 33 11 D Q 1 D Q 2 A 4 D Q 3 D Q 4 A 3 D Q 5 D Q 6 A 2 D Q 7 D Q 8 A 1 D Q 9 D Q 1 0 A 0 D Q 1 1 D Q 1 2 A 1 5 D Q 1 3 D Q 1 4 A 1 4 D Q 1 5 D Q 1 6 A 1 3 A 1 2 A ...

Page 45: ...E _ S C K E E _ C S H R W H D S H C S H R E Q H A C K S S M I S O M O S I S C K H D 0 H D 2 H D 4 H D 6 H A 0 H A 2 H D S H R E Q H D 1 H D 3 H D 5 H D 7 H A 1 H R W H C S H A C K 3 3V 3 3V 3 3V 3 3V R 5 4 1 0 K R 5 6 1 0 K J G 1 0 1 3 5 7 2 4 6 8 U 4 A T 4 5 D B 0 1 1 B S C 1 8 4 6 3 5 7 2 SI S O C S V C C R E S E T W P G N D S C K R 5 3 1 0 K R 5 5 1 0 K R 5 8 1 0 K R 5 7 1 0 K R 5 9 1 0 K J4 1 ...

Page 46: ...I N R X T3IN T X D 0 R X D 0 3 3V 3 3V 3 3V R 5 1 1 K R 5 2 1 K R 5 0 1 K R 4 9 1 K R 4 6 1 K R 4 5 1 K J G 9 1 2 R 4 7 1 K T4 1 T5 1 T6 1 T7 1 P 3 5 9 4 8 3 7 2 6 1 T2 1 T1 1 T8 1 T3 1 U 5 M A X 3 2 4 5 E E A I 27 1 26 2 23 28 14 13 12 19 18 17 16 15 8 7 6 5 4 11 10 9 22 24 3 25 20 21 V C 2 V C C C2 F O R C E O N C 1 T1IN T2IN T3IN R 1 O U T R 2 O U T R 3 O U T R 4 O U T R 5 O U T R 5 I N R 4 I N...

Page 47: ...0 S C 0 2 S C 0 1 S C 0 0 R X D1 TXD1 5 0VA 3 3V 3 3V 3 3V 3 3V 5 0VA R 2 0 5 62K 1 C 9 0 47uF R 2 7 3 9 2K 1 R 2 3 5 62K 1 C 1 1 0 47uF R 2 5 5 62K 1 C 7 0 0022uF R 2 8 39 2K 1 C 4 470pF C 8 0 0022uF R 1 9 5 62K 1 C 1 0 0 47uF R 3 2 1K R 3 4 10K R 3 5 10K R 3 8 10K R 3 3 1K R 3 0 10K R 3 1 10K R 2 9 10K R 2 6 10K R 2 4 10K R 2 2 10K R 2 1 10K C 1 3 0 1uF C 1 2 4 7 uF 1 0 V D C R 3 6 10K C 3 1 u F...

Page 48: ... SET J_TRST T D O P _ D E P _ DE DE TDI TDO TCK TMS RESET TRST P O R DE 3 3V 3 3V 3 3V 3 3V 3 3V R 7 51 Oh m R 1 4 5 1K R 1 3 5 1K J 3 1 3 5 7 9 1 1 1 3 2 4 6 8 1 0 1 2 1 4 R 1 5 47K R 1 1 47K R 1 270 R 3 270 R 2 270 R 5 270 R 4 270 R 1 0 5 1K J G 5 1 2 U 9 MC74LCX244D W 1 8 1 6 1 4 1 2 9 7 5 3 1 9 1 2 4 6 8 1 1 1 3 1 5 1 7 2 0 1 0 1 Y 1 1 Y 2 1 Y 3 1 Y 4 2 Y 1 2 Y 2 2 Y 3 2 Y 4 2 G 1 G 1 A 1 1 A ...

Page 49: ...A 1 4 R D W R D 1 D 3 D 5 D 7 D 9 D 1 3 D 1 5 A 5 A 7 A 9 A 1 3 A 1 5 C S 0 A 1 C S 1 A 1 0 A 1 1 A 1 2 A 3 A 4 D 1 0 D 1 1 D 1 2 M I S O S C K S R D 0 S C 0 1 R E S E T IRQA M O S I S S R X D 0 S T D 0 S C K 0 IRQB C L K O TXD0 A 1 9 A 2 0 A 1 8 A 1 6 C S 3 C S 2 A 1 7 T I O 0 T I O 1 R X D 1 TXD1 C S 0 C S 1 C S 2 C S 3 S C 0 0 S C 0 2 S R D 1 S C 1 1 S C K 1 S C 1 0 S C 1 2 S T D 1 M O D A M O ...

Page 50: ... 4 6 4 4 1 4 1 5 1 6 1 8 2 0 2 1 2 2 2 3 2 5 2 6 2 7 2 8 3 0 3 1 3 3 3 4 4 3 4 2 3 2 1 7 5 7 5 4 6 0 6 3 1 9 2 4 2 9 6 2 4 5 1 0 4 7 1 1 1 2 5 9 5 3 4 9 3 5 1 2 6 4 3 5 8 5 6 5 5 4 8 9 4 1 6 1 5 0 5 2 5 1 4 0 3 9 3 8 1 3 3 6 3 7 L A 0 L A 1 L A 2 L A 3 L A 4 C S I O R L D 0 L D 1 L D 2 L D 3 L D 4 L D 5 L D 6 L D 7 L D 8 L D 9 L D 1 0 L D 1 1 L D 1 2 L D 1 3 L D 1 4 L D 1 5 R E S E T V D D C 2 V D...

Page 51: ... 0V 5 0 V A 3 3V 3 3V V C C 1 8V 5 0V 5 0V C 5 4 0 1uF C 5 8 0 1uF U 1 3 M C 3 3 2 6 9 D T 3 3 3 2 4 1 V I N V O U T V O U T G N D L1 F E R R I T E B E A D L4 F E R R I T E B E A D L3 F E R R I T E B E A D C 5 5 4 7 u F 1 0 V D C R 8 3 270 C 5 6 0 1uF U 1 4 M C 3 3 2 6 9 D T A D J 3 2 4 1 V I N V O U T V O U T G N D R 8 1 243 1 R 8 2 107 1 C 5 9 4 7 u F 1 0 V D C L2 F E R R I T E B E A D C 5 7 4 7...

Page 52: ...d Tempe Arizona 85284 Title Document Date Size Designer Sheet of Rev Number 480 413 5090 FAX 480 413 2510 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 1 8 V 1 8 V 1 8 V 1 8 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 5 0 V A 3 3 V 3 3 V 5 0 V A 3 3 V 1 8 V 1 8 V 1 8 V 3 3 V C 3 4 0 01uF C 3 5 0 1uF C 3 2 0 01uF C 2 8 0 01uF C 3 0 0 01uF C 2 6 0 01uF C 2 9 0 1uF C 2 7 0 1uF C 3 1 0 1...

Page 53: ...7 Epson SG 531P 12 288MC 1 LM4880 U8 National Semiconductor LM4880M 1 74LCX244 U9 ON Semiconductor MC74LCX244ADW 1 74AC00 U10 Fairchild 74AC00SC 1 74AC04 U11 ON Semiconductor MC74AC04AD 1 5 0V Voltage Regulator U12 ON Semiconductor MC33269DT 5 1 3 3V Voltage Regulator U13 ON Semiconductor MC33269DT 3 3 1 1 8V Voltage Regulator U14 ON Semiconductor MC33269DT ADJ 1 NET2270 U15 NetChip NET2270 1 DS18...

Page 54: ...73L2A20 0KOHMFT 2 R42 R43 SMEC RC73JP2A 0 R44 SMEC RC73JP2A 0 10K R68 SMEC RC73L2A10KOHMJT 3 470K R69 R70 R74 SMEC RC73L2A470KOHMJT 1 R81 SMEC RC73L2A243OHMFT 1 107 R82 SMEC RC73L2A107OHMFT 2 35 7 R84 R85 SMEC RC73L2A35 7OHMFT 1 1 5K R86 SMEC RC73L2A1 5KOHMJT 1 1M R87 SMEC RC73L2A1MOHMJT 1 9 09K R89 SMEC RC73L2A9 09KOHMFT Inductors 4 1 0mH FERRITE BEAD L1 L4 Panasonic EXC ELSA35V 5 FERRITE BEAD L5...

Page 55: ... C13 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C44 C46 C48 C50 C52 C54 C56 C58 C67 C68 C72 SMEC MCCE104K2NR T1 18 0 01PF C26 C28 C30 C32 C34 C36 C38 C40 C42 C45 C49 C51 C60 C64 C66 C70 C71 SMEC MCCE103K2NR T1 1 470PF 16V DC C53 ELMA RV 16V471MH10R 2 15pF C61 C62 SMEC MCCE150J2NO T1 Jumpers 4 1 u 2 2mm Header JG1 JG5 JG9 JG11 SAMTEC TMM 102 02 S S 2 2 x 2 2mm Header JG2 JG8 SAMTEC TMM 102 02 S D ...

Page 56: ...tchcraft RAPC 722 1 DE9S Connector P3 AMPHENOL 617 C009S AJ120 3 1 8 Stereo Jack P4 P6 Switchcraft 35RAPC4BHN2 2 51 Pin HD Connector J1 J2 BERG 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 10 x 2 RT Bergstick J4 SAMTEC TSW 110 07 S D RT 1 Type B USB J5 Mill Max 897 30 004 90 000000 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton S1 S3 Panasonic EVQ P...

Page 57: ...2 2 interconnection diagram 1 4 ISSI compatible peripheral 2 2 JTAG port interface 2 1 Memory Daughter Caard Expansion Connector 2 2 On board power regulation 2 2 Parallel JTAG Host Target Interface 2 1 power connection cable connection 1 4 real time debugging 2 8 RS 232 interface 2 1 SCI compatible peripheral 2 2 SPI compatible peripheral 2 2 test points 2 23 USB interface 2 2 E EEPROM Preface ix...

Page 58: ...face ix RS 232 interface 2 1 2 6 level converter 2 6 schematic diagram 2 6 RS 232 Serial Communications 2 6 S SCI Preface ix SPI Preface x SRAM Preface x external data 2 1 external program 2 1 SSI Preface x stereo 16 bit codec interface 2 1 Stereo headphone interface 2 1 T THD Preface x U USB Preface x 2 22 schematic diagram 2 22 W WS Preface x ...

Page 59: ......

Page 60: ...cuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product o...

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