nvent Schroff 14579-040, User Manual

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14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 9
3.4.1 Clock specifications
For all specifications not mentioned in the tables below refer to the PXI-1 und PXI-5 PXIe
Hardware specifications
PXI_CLK10
Maximum slot to slot time skew 500 ps

Note: PXI-5 spec specifies 1 ns
Frequency accuracy ±25 ppm max (guaranteed over the operating temperature range)

Note: PXI-5 spec specifies ±100 ppm
Maximum jitter 5 ps RMS phase jitter (10 Hz – 10 MHz range)
Duty factor 45 % to 55 %
Unloaded signal swing 3.3 V ±0.3 V
Values above valid for PXI standard products. Optimized parameters are possible on
request (Jitter
≤ 2 ps, Accuracy 2 ppm, slot-to-slot skew 100 ps)
PXIe_CLK100 and PXIe_SYNC100
Maximum slot to slot time skew 80 ps
Note: PXI-5 spec specifies 200 ps
Frequency accuracy ±25 ppm max (guaranteed over the operating temperature range)

Note: PXI-5 spec specifies ±100 ppm
Maximum jitter 5 ps RMS phase jitter (10 Hz – 20 MHz range)
Duty factor 45 % to 55 %
Absolute differential voltage when each line pair is ter-
minated with a 50

load to 1.30 V (or Thevenin equiva-
lent)
500 mV to 950 mV
Values above valid for PXI standard products. Optimized parameters are possible on
request (Jitter
≤ 2 ps, Accuracy 2 ppm)
External 10 MHz Reference In
Frequency 10 MHz ±50 ppm
Input amplitude 200 mV to 5 V, square wave or sine wave
Maximum jitter introduced by backplane 1 ps RMS phase jitter (10 Hz – 10 MHz range)
Rear panel BNC connector input impedance 50

±5

External 10 MHz Reference Out
Frequency accuracy ±25 ppm max.
(guaranteed over the operating temperature range)
Maximum jitter 5 ps RMS phase jitter (10 Hz – 10 MHz range)
Output amplitude min. 1.2 Vpp square wave into 50

min. 2.9V unloaded
Output impedance 50

±5
