nvent Schroff 14579-040, User Manual

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14579-040 (PXIe System)
8 18 Slot PXIe Backplane (23007-518) R1.5, January 2021
3.4 System Synchronisation Clocks
Acc. to the PXI specifications, the Schroff PXIe system routes the PXI_CLK10 to slot 1-18 and
PXIe_CLK100 and PXIe_SYNC100 to the peripheral slots 2-18.
PXI_CLK10 is also routed to the external BNC connector 10 MHz REF OUT at the chassis rear
side.
All clocks/timing signals are generated by the PXI-5 compliant Schroff PXIe Clock Module.
When a 10 MHz reference clock signal is present at the System Timing Slot or the rear panel
connector 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are phase-locked to
this reference clock signal according to the following table:
The source for the reference signal is selected automatically, if a 10 MHz reference clock is
present at the System Timing Slot
and the external clock input, the signal from the System
Timing Slot is selected.
Mode System Timing Slot Ext. 10 MHz REF In Backplane Clock Module
1 10 MHz clock present 10 MHz clock present 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
phase-locked to reference clock signal from
System Timing Slot
1 10 MHz clock present - 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
phase-locked to reference clock signal from
System Timing Slot
2 - 10 MHz clock present 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
aphase-locked to reference clock signal from
Ext. 10 MHz REF In
3 - - 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
generated by the Clock Module
P
X
I_CLK
1
0
P
X
Ie
_CL
K10
0
P
X
Ie
_S
YN
C1
0
0
XO
10 MHz
10 MHz
REF IN
PLL Buffer
Buffer
Buffer
Auto-mode:
1 -> 2
2
I2C-Control
10 MHz
REF OUT
Slot 1
Slot 2 Slot n
Schroff PXIe Clock Module
3
1
Timing Slot
-> 3