Numark D2 Director, Service Manual

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LCD backlight control
IC10 and associated components provide an adjustable voltage to drive the LCM backlight. The
signal BRIGHT is a PWM signal from the ARM CPU. R67/R69/C15 scales and filters this to a DC
level, which connects to the adjust pin of the voltage regulator IC10. IC10 will act so as to maintain
1.25V between its output and adjust pin, therefore the output will follow 1.25V above the adjust
pin. This drives the LCM backlight.
Core supply and power sequencing
IC11 is an adjustable voltage regulator providing the 1.8V core supply for the ARM CPU.
The ARM CPU needs the I/O supply to come up some time before the core supply. If this is not
done, the CPU sometimes fails to boot up due to a bug in the IC. To achieve this, a power
sequencing circuit is employed to turn off the input to IC11 for a short time at power up.
IC16 is a reset generator IC, the output of which will stay low for approximately 240ms after the
3.3V rail comes up. This signal is inverted by TR1 and then controls the gate of MOSFET TR2.
TR2 will therefore be off for 240ms after power up, so the 1.8V core supply will come up 240ms
after the 3.3V rail.
SHEET 3 – DSP
This sheet shows the SHARC DSP IC13, which is used for some of the audio processing. Audio
from the ARM is processed before being transmitted to the codec. Audio from the codec is
processed before being transmitted to the ARM (the latter is not used in the NH00).
The DSP uses a 1.2V core provided by regulator IC18. The I/O supply is 3.3V. IC15 is a
22.5792MHz oscillator used by the DSP to generate all the clocks in needs internally using phase
locked loops.
The software for the DSP is loaded shortly after power up using the SPI bus, as described earlier.
Configuration resistors R84, R82 and R85 are important and ensure the DSP boot in the correct
mode with the correct internal clock frequency.
Audio interfaces
The DSP has audio interfaces to the ARM and the codec. In both cases the DSP is the I2S master.
The interface with the ARM is descibed earlier.
The following signals make up the interface with the codec, these run at 44.1kHz sample rate.
Signal Name Function Source
DSP-BCLK I2S bit clock (2.8224MHz) DSP
DSP-MCLK I2S master clock (11.2896MHz) DSP
DSP-LRCLK I2S word clock (44.1kHz) DSP
DSP-SIN0 I2S data in channel 0 (not used in NH00) CODEC
DSP-SIN1 I2S data in channel 1 (not used in NH00) CODEC
DSP-SOUT0 I2S data out channel 0 (deck A) DSP
DSP-SOUT1 I2S data out channel 1 (deck B) DSP
DSP-SOUT2 I2S data out channel 2 (not used in NH00) DSP
Status LED
D5 is a red LED that shows the status of the DSP. Normally, this will turn on at power up, then turn
off while the software is loaded into the DSP, before turning on again once the software starts
running. If the behaviour is different then it indicates a problem with the DSP.