20
•
Registers Format
0
1
10
±
1V
±
500mV
1V
1
0
100
±
100mV
±
50mV
100mV
4.6 A/D Status Readback Register
The A/D FIFO status can be read back from this register.
Address:
BASE + 2
Attribute:
read only
Data Format:
Bit
7
6
5
4
3
2
1
0
BASE+2
X
X
X
X
AD_BUSY
FF_FF
FF_HF
FF_EF
BASE+3
X
X
X
X
X
X
X
X
FF_EF: ‘0’ means FIFO is empty
FF_HF: ‘0’ means FIFO is half-full
FF_FF: ‘0’ means FIFO is full, A/D data may have been loss
AD_BUSY:‘0’ means AD is busy, the A/D data has not been latched in
FIFO yet. If AD_BUSY changes from ‘0’ to ‘1’, A/D data is written into FIFO.
4.7 A/D Trigger Mode Control Register
This register is used to control or read back the A/D trigger control setting
and the A/D range setting.
Address:
BASE + 4
Attribute
:
write and read
Data Format:
Bit
7
6
5
4
3
2
1
0
BASE+4
X
X
X
X
G1
G0
TSSEL
ASCAN
BASE+5
X
X
X
X
X
X
X
X
G0~G1: A/D range setting, read back (only)
TSSEL: Timer Pacer / Software Trigger
1: Timer Pacer Trigger
0: Software Trigger
ASCAN: Auto Scan Control
1: Auto Scan ON
0: Auto Scan OFF
Summary of Contents for PCI- 9113A
Page 1: ...N u D A Q P C I 9 1 1 3 A 32 Channels Isolated Analog Input Card User s Guide ...
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Page 16: ...6 Introduction now The PCIS OPC supports the Windows NT It needs license ...
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Page 62: ...52 C C Software Library Return Code ERR_NoError ...
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