NuDAQ PCI-8554, User Manual, Page: 10 / 62

2
•
Introduction
PCI-8554 uses ASIC PCI controller to interface the board to the PCI
bus. The ASIC fully implement the PCI local bus specification Rev 2.0.
All bus relative configurations, such as base memory and interrupt
assignment, are automatically controlled by BIOS software. It does
not need any user interaction and pre-study for the configurations.
This removes the burden of searching for a conflict-free configuration,
which can be very time consuming and difficult with some other bus
standards.
Figure 1.1. Block diagram of the PCI-8554
1.1 Features
The PCI-8554 Counter / Timer and digital I/O Card provides the
following advanced features:
•
Four 8254 chips provide twelve 16 bits down counters
•
Multi-configurations of counters / timers:
•
Flexible setting for each independent counter, the clock source
could be external, internal or cascaded. The gate signal is
external controlled or internal enabled.
•
Provide debounce function with flexible setting to prevent from
bounce p henomenon when using external clock.
•
8 digital output channels
•
8 digital input channels
•
Dual interrupt sources
The first interrupt source comes from output of counter#12
PCI Bus
P C I
C o n t r o l l e r
data
b u s
A d d r e s s
bus
Interrupt
Interrupt
s y s t e m
clock
system
100
pin SCSI-II
8 bits digital
i n p u t / o u t p u t
8254
chip #1
8254
chip #2
8254
chip #3
8254
chip #4
8
8
C O U T 1 ~ C O U T 3
G A T E 1 ~ G A T E 3
C O U T 4 ~ C O U T 6
G A T E 4 ~ G A T E 6
C O U T 7 ~ C O U T 9
G A T E 7 ~ G A T E 9
C O U T 1 0 o n l y
G A T E 1 0 o n l y
D e b o u n c e
s y s t e m
E C L K 1 ~ E C L K 1 0
E _ I N T
C O U T 1 2