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NPM Motionnet G9001A, User Manual

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NPM Motionnet G9001A User Manual Download Page 14

DA70131-1/3E

 

I-8

 

4-2. Terminal allocation diagram 

 

 

 
 
 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 

Note: For each pin number, see the marks on the actual LSI. 

As shown above, to the lower left of the NPM logo mark is the 1st pin. 

 
 
 
 

G9001A 

D12 

GND 

D11 

D10 

D9 

D8 

VDD 

D7 

D6 

D5 

D4 

GND 

D3 

D2 

D1 

D0 

1 

2 

3 

4 

5 

6 

16 

7 

8 

9 

10  11  12  13  14  15 

49 

50 

51 

52 

53 

54 

55 

56 

57 

58 

59 

60 

61 

62 

63 

64 

32 

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

18 

17 

48  47  46  45  44  43  42  41  40  39  38  37  36  35  34  33 

 

XXXXXXXXX 

JAPAN 

SPD0 

SPD1 

SIA 

GND 

VDD 

SIB 

GND 

CKSL 

GND 

CLK 

VDD 

GND 

GND 

GND 

____

 

RST 

VDD 

V

DD

 

SO

 

SO

EH

 

____

_

 

SO

EL

 

M

SYN

 

____

_

 

M

E

RF

 

G

N

D

 

____

_

 

M

E

RR

 

____

_

 

M

C

RY

 

____

 

IFB

 

____

 

W

RQ

 

____

 

INT

 

V

DD

 

D1

5

 

D1

4

 

D1

3

 

IF0

 

IF1

 

___

 

CS

 

___

 

WR

 

___

 

RD

 

A0

 

A1

 

A2

 

A3

 

G

N

D

 

A4

 

A5

 

A6

 

A7

 

A8

 

V

DD

 

  

 

Summary of Contents for Motionnet G9001A

Page 1: ...DA70131 1 3E G9001A G9002A User s Manual Center device I O device Remote I O Remote Motion...

Page 2: ...ot responsible for any results that occur from using this LSI regardless of item 3 above 5 Please see the latest version on our website Cautions As a next generation communication system the Motionnet...

Page 3: ...8 3 Register access command I 28 4 9 Register I 29 4 9 1 RENV0 register I 29 4 9 2 RERCNT I 30 4 9 3 RSYCNT I 30 4 9 4 RDJADD I 30 4 9 5 RVER I 30 5 Description of the software I 31 5 1 Outline of con...

Page 4: ...stics II 12 5 1 Absolute maximum ratings II 12 5 2 Recommended operating conditions II 12 5 3 DC characteristics II 12 5 4 AC characteristics II 13 5 4 1 Reference clock II 13 5 4 2 Reset timing II 13...

Page 5: ...vice IV 15 2 8 Data communication 2 Read a register in a PCL device IV 16 2 9 Data communication 3 Start the PCL device IV 17 2 10 Data communication 4 Start a PCL6045B using a CPU emulation device IV...

Page 6: ...communication control terminal VIII 1 1 2 Function of I O port terminal VIII 1 2 Difference of electrical Characteristics VIII 2 2 1 Absolute maximum ratings VIII 2 2 2 Recommended operating condition...

Page 7: ...DA70131 1 3E I 1 I Center device G9001A User s Manual...

Page 8: ...DA70131 1 3E I 2...

Page 9: ...data transfer speed is 20 Mbps Transfer cycle time is less than 1 msec when 64 local devices are connected in case of cyclic communication only One center device can connect up to 256 ports 2048 bits...

Page 10: ...duty approximate to the ideal one will be established Even if the ideal duty is broken a little when signal lines are shorter and or the number of local devices is smaller the center device can opera...

Page 11: ...range 40 to 85 C Note By issuing an operation command to the center device you can access the entire address area through a single I O buffer It will take more time than direct access Required addres...

Page 12: ...S 23 D5 B Positive Data bus bit 5 5V S 24 D6 B Positive Data bus bit 6 5V S 25 D7 B Positive Data bus bit 7 5V S 27 D8 B Positive Data bus bit 8 5V S 28 D9 B Positive Data bus bit 9 5V S 29 D10 B Posi...

Page 13: ...ed to 5 5V CMOS TTL LVTTL and so on However the connection of over 3 3V to output cannot be available For example output with 5V pull up resistors cannot be 5V CMOS Note 3 As for the terminals with 5V...

Page 14: ...3 4 5 6 16 7 8 9 10 11 12 13 14 15 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XXXXXXXXX JAPAN SPD0...

Page 15: ...receiving FIFO Serial signal receiving circuit Receipt data processing circuit Transfer processing circuit Data transfer FIFO Serial signal transfer circuit SIA SIB Internal clock 20MHz Internal cloc...

Page 16: ...ncy If you do not want to use 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI 4 4 2 ____ RST This is an input terminal for a reset signal By inputting an L level signal the...

Page 17: ...Enter address signal to these terminals When the IF1 is L address bus A1 to A8 are inverted inside When to control at 8 byte area process as follows IF1 terminal status A 8 3 process Remarks L Pull up...

Page 18: ...r to prevent this problem separate to two lines Even divided into two lines use easiness from a CPU is identical One line can connect to max 64 devices Even when two lines are used the max number of d...

Page 19: ...ch with the local device status such as receiving output data on the input port It may possible because of the mistakes from the CPU In this case the local device sends back the data to the center dev...

Page 20: ...mmunication error flags Device No 0 to 7 Cyclic communication error flags Device No 0 to 7 0 1011 1001 0B9h Cyclic communication error flags Device No 8 to 15 Cyclic communication error flags Device N...

Page 21: ...ce No 63 Port 0 1 1111 1101 1FDh Port data No 253 Device No 63 Port 1 Port data No 253 Device No 63 Port 1 1 1111 1110 1FEh Port data No 254 Device No 63 Port 2 Port data No 254 Device No 63 Port 2 1...

Page 22: ...ror flags Device No 48 to 63 Cyclic communication error flags Device No 48 to 63 0 1100 000 0C0h Input change interrupt settings Device No 0 to 3 Input change interrupt settings Device No 0 to 3 0 110...

Page 23: ...error flags Device No 48 to 63 Cyclic communication error flags Device No 48 to 63 1 0011 111 13Eh Input change interrupt settings Device No 0 to 3 Input change interrupt settings Device No 0 to 3 1...

Page 24: ...equired for each device 7 6 5 4 3 2 1 0 0 0 0 Device information I O setting Set value Port0 Port1 Port2 Port3 PMD2 PMD1 PMD0 000 Output Output Output Output 001 Input Output Output Output 010 Input I...

Page 25: ...same way by reading 0BAh you can check device numbers 16 to 31 To determine the address proceed as follows discard any remainder Address 0B8h Device No 8 For an 8 bit CPU address 0B8h 7 6 5 4 3 2 2 1...

Page 26: ...The lowest 4 bits will be the area for setting up input change interrupts for the local device with the lowest address number The lowest of the 4 bits corresponds to port 0 the next bit corresponds to...

Page 27: ...cept that data will be handled in units of 8 bits To clear flags In order to return a bit to 0 that was changed to a 1 when a change occurred I the input write a 1 to this bit The simplest way to clea...

Page 28: ...nditions of the error to be occurred see 2 Data communication errors in section 5 1 5 The method for clearing this bit will depend on status bit 9 in the RENV0 register 5 ERAE Note 1 Becomes 1 when a...

Page 29: ...Always 0 12 SBSY Becomes 1 when cyclic communication starts 13 RBSY Is 1 during a reset 14 DBSY Is 1 during system communication or data communication 15 BBSY When RENV0 8 is 1 and the center device...

Page 30: ...en this error occurs the center device will store one of the following codes in these bits This condition is stored until the next time an error occurs Code Error conditions 0001 I O setting informati...

Page 31: ...ollowing meaning 0 CAER ERAE EDTE 0 0 BRKF CEND By changing each of these bits to 1 the corresponding status will be cleared However if RENV0 9 0 the clear command will be ignored 0000 0110 0000 0000...

Page 32: ...le 0001 0011 00 1300h to 133Fh Obtain attribute information for the specified devices The polling response frame consists of device attribute information This command polls the specified devices and c...

Page 33: ...word of the above area 0110 0000 0 xx 6000h to 607Fh Reads the device information area The contents of one word in the above area are copied to the input output buffer 0110 0001 0 x xxxx 6100h to 617F...

Page 34: ...101 0000 0010 6502h Cyclic cycle register read command When this command is issued the value of the cyclic cycle register is copied to the input output buffer Reading the input output buffer you can o...

Page 35: ...INT group status clear command 04xxh After a reset all the bits will be zero 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 MCLR 0 MCSE MERE MEDE MEIE MIOP MBRK MCED Bit Bit name Details 0 MCED...

Page 36: ...r counts up to 65535 approx 65 5 ms The center device cannot measure the time if the MSYN signal length exceeds this value 4 9 4 RDJADD This register latches the device address for the most recently r...

Page 37: ...nse from the local devices 8 bits are used for the device information about each device 7 6 5 4 3 2 1 0 0 0 0 Device information I O setting Set value Port0 Port1 Port2 Port3 PMD2 PMD1 PMD0 000 Output...

Page 38: ...at the center device can read the data until receiving FIFO is emptied If data communication commands are written continuously further data communication will be postponed until another round of cycli...

Page 39: ...pplying a HIGH to the terminal for a certain length of time to create a break signal the local device will enter the break waiting status Also the center device periodically sends a break frame sendin...

Page 40: ...t cleared by reading 3 Other error processing 1 When a local device detects an error in the receiving frame such as a CRC error it does not respond 2 When any of the following errors occurs in a local...

Page 41: ...tus bit 10 RDBB returns to 0 the center device will read the response data from the data receiving FIFO Note 1 While cyclic communication is stopped data communication is disabled Note 2 Writing a sen...

Page 42: ...When there is no data in the response from a local device Basic item Required time s Data sending time ST B x 0 6 3 25 x K Response time with data JT B x 0 6 5 65 x K Response time without data JT 5 0...

Page 43: ...3 to VSS 0 3 V Input voltage 5V I F VIN VSS to 5 8 V Storage temperature Ta 40 to 85 o C 7 3 DC characteristics Item Symbol Condition Min Max Unit Current consumption Idd CLK 80 MHz 45 mA Output leaka...

Page 44: ...Clock cycles Delay time TDRST 10 Clock cycles Note 1 The reset signal must last at least 10 cycles of the reference clock While resetting make sure that the clock signal is continuously available to t...

Page 45: ...___ RD ____ WR TARW 18 ns Address hold time for ___ RD ____ WR TRWA 0 ns ____ CS setup time for ___ RD ____ WR TCSRW 8 ns ____ CS hold time for ___ RD ____ WR TRWCS 0 ns _____ WRQ ON delay time for _...

Page 46: ...___ RD ____ WR TARW 18 ns Address hold time for ___ RD ____ WR TRWA 0 ns ____ CS setup time for ___ RD ____ WR TCSRW 8 ns ____ CS hold time for ___ RD ____ WR TRWCS 0 ns _____ WRQ ON delay time for _...

Page 47: ...___ RD ____ WR TARW 18 ns Address hold time for ___ RD ____ WR TRWA 0 ns ____ CS setup time for ___ RD ____ WR TCSRW 8 ns ____ CS hold time for ___ RD ____ WR TRWCS 0 ns _____ WRQ ON delay time for __...

Page 48: ...S hold time for ____ LS TSCS 0 ns R ___ W setup time for ____ LS TRWS 2 ns R ___ W hold time for ____ LS TSRW 14 ns _______ DTACK ON delay time for ____ LS TSLAKR CL 40pF Note 1 2TCLK 14TCLK 15 ns TSL...

Page 49: ...DA70131 1 3E I 43 8 External dimensions Plastic QFP13 64pin Unit mm 1 7max 1 64 12 0 4 10 0 1 12 0 4 0 5 0 18 0 1 0 125 10 0 1 0 1 0 025 0 05 0 025 G9001A XXXXXXXXX JAPAN 1 4 0 1 0 10 0 5 0 2 1...

Page 50: ...DA70131 1 3E I 44...

Page 51: ...DA70131 1 3E II 1 II I O device G9002A User s Manual...

Page 52: ...DA70131 1 3E II 2...

Page 53: ...logic can be specified for each I O port Specify the logic using the LSI terminals A single 3 3 V power source is all that is needed Connections can be made to 5 V devices on the main terminals 3 Basi...

Page 54: ...n port 0 5V 17 P04 B Bit 4 on port 0 5V 18 P05 B Bit 5 on port 0 5V 19 P06 B Bit 6 on port 0 5V 20 P07 B Bit 7 on port 0 5V 23 _____ P1N I Negative LOW Sets P10 to P17 to use negative logic 5V 24 P10...

Page 55: ...it 4 5V 77 _____ DN3 I Negative Device number bit 3 5V 78 _____ DN2 I Negative Device number bit 2 5V 79 _____ DN1 I Negative Device number bit 1 5V 80 _____ DN0 I Negative Device number bit 0 common...

Page 56: ...5 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 G9002A XXXXXXXXX JAPAN XXXX _____ DNSO DNSM ____ RST BRK SOEI _...

Page 57: ...vice number G9002A P0 7 0 P1 7 0 P2 7 0 P3 7 0 SPD 1 0 CLK CKSL Watchdog timer Clock control Manage level output I O control 20 MHz 40 MHz ______ DNSO Device number Port data Timing signal ______ TOUT...

Page 58: ...this case select 80 MHz The center device divides the frequency inside and creates 40 MHz frequency If you do not want to 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI 4...

Page 59: ...ection When the data transmission interval from a center device to this device exceeds the set time the watchdog timer times out This terminal is used to set output conditions when the watchdog timer...

Page 60: ...ime 4 4 17 BRK By providing HIGH pulses that are longer than the specified interval the I O device will be made to wait for a break frame When the I O device receives a break frame send request from a...

Page 61: ...dinary high low output This setting specifies all output ports Input output ports that are used as input ports are not specified by this setting OPDSL Mode Function Low G9002 compatible mode Open drai...

Page 62: ...based on the condition TJ 40 to 125 C 5 3 DC characteristics VSS 0V Item Symbol Condition Min Max Unit Current consumption Idd CLK 80 MHz 33 5 mA Output leakage current IOZ 1 1 A Input capacitance 10...

Page 63: ...2 When setting CKSL H Item Symbol Min Max Unit Frequency fCLK 80 MHz Cycle TCLK 12 5 ns HIGH duration TCLKH ns LOW duration TCLKL ns 5 4 2 Reset timing Item Symbol Min Max Unit Reset length TWRSTI 10...

Page 64: ..._ MSEL is HIGH so that you can get reliable data 5 4 4 Input data set timing The I O device reads the data input on the ports using basically the same timing for the output data It sends the data it r...

Page 65: ...31 1 3E II 15 6 External dimensions 80 pin LQFP Unit mm 1 80 14 0 4 12 0 1 0 5 1 4 0 1 1 7max 0 1 0 08 0 3 min 0 75 max 14 0 4 12 0 1 0 10 G 9 0 0 2 A XXXXXXXXX J A P A N 0 09 min 0 2 max 0 13 min 0 2...

Page 66: ...DA70131 1 3E II 16...

Page 67: ...DA70131 1 3E III 1 III Connection Examples and Recommended Environments G9000 Series...

Page 68: ...DA70131 1 3E III 2...

Page 69: ...vector At this time when this LSI s ____ CS terminal goes LOW the LSI may output a ____ WRQ signal and still not be able to capture the vector properly Therefore arrange the decoding circuit so that...

Page 70: ...e lines to the decoding circuit and use them to create the ___ CS signal A0 to A2 Connect these lines to A0 to A2 on the center device Connect A3 to A8 on the center device to GND G9001A 8086 type CPU...

Page 71: ...ines to the decoding circuit and use them to create the ___ CS signal A0 to A2 Connect these lines to A0 to A2 on the center device A3 to A8 on the center device should be pulled up Decoding circuit G...

Page 72: ...uit and use them to create the ___ CS signal A0 to A2 Connect these lines to A0 to A2 on the center device A3 to A8 on the center device should be pulled up G9001A 68000 type CPU Decoding circuit CLK...

Page 73: ...ons In the example above the ____ IFB output terminal on the center device is connected to a port on the 8031 The ____ IFB bit is monitored using a routine in the 8031 so that the 8031 does not try to...

Page 74: ...1 Write to the I O buffer or the data transfer FIFO The timing for writing to the I O buffer address 4 and 5 when I F mode 4 or the data transfer FIFO address 6 and 7 when I F mode 4 is shown below A...

Page 75: ...F mode 4 and the memory area 078h to 1FFh when the I F mode 4 is shown below When reading the I O buffer addresses 4 and 5 when the I F mode 4 no waiting time is needed A wait of 4 clock cycles or lon...

Page 76: ...enter device has 9 address terminals used to access 512 bytes of memory The access timing for each of these addresses is shown below However for certain CPUs this amount of memory is not directly avai...

Page 77: ...cycles or longer to perform continuous writing at 40 MHz 1 Does not use the ____ WRQ output CPU does not have a wait function 2 Uses the ____ WRQ output CPU has a wait function Command Address Next ad...

Page 78: ...d area The following operations both read and write require intervals of at least 8 clock cycles at 40 MHz The data can be written in any order However the commands must be written in low bit high bit...

Page 79: ...eference CLK cycles at 40 MHz before the data can be read by the CPU When reading data from the I O buffer there is no restriction on the timing It can be read in any order Read commands must be writt...

Page 80: ...d If there are only a few local devices and the serial line is relatively short a single one of the input lines named above will be enough to maintain a reliable signal If you will not be using one or...

Page 81: ...which match the cable impedance at both ends of the transmission line The terminating resistors can be either before or after the pulse transformer The same effect will be obtained at either position...

Page 82: ...GND Terminating resistor Device number VDD Local device Local device 1000 H or equivalent Pulse transformer Using the connections shown below the address of the local device above will be the address...

Page 83: ...A SO SOEH Center device Line transceiver Transformer Transformer SI SO SOEH Local device Transformer SI SO SOEH Local device Transformer SI SO SOEH Local device Transformer SI SO SOEH Local device If...

Page 84: ...total length of the line LAN cables normally consist of several pair of wires Make sure to use wires from the same pair for one set of communication lines Even when using cables with the same category...

Page 85: ...formers with a larger reactance Line transceivers We recommend you using 5V line transceiver because a 5V line transceiver has higher performance than 3 3V one Connectors If possible the connectors sh...

Page 86: ...ne system Do not mix cables from different manufacturers even when they are in the same category Different cable models from the same manufacturer should not be used either Using different cables toge...

Page 87: ...DA70131 1 3E IV 1 IV Software Examples flow chart G9001A...

Page 88: ...DA70131 1 3E IV 2...

Page 89: ...sumption that the wiring connections around the center device have been properly prepared and that the connected local devices are turned on And of course we presume that connections to the serial lin...

Page 90: ...it the steps needed to process errors Be aware that when actually creating programs you will have to add steps for processing errors We recommend creating the steps used to check errors after reading...

Page 91: ...tation Local device type Device No Input port Output ports 1 I O device 10 Port 0 Port 1 to 3 2 PCL device 11 Port 0 to 2 Port 3 3 I O device 20 Port 0 to 2 Port 3 Note The port attributes of the PCL...

Page 92: ...Start Outpw 0x0004h 0x0083h Outpw 0x0000h 0x5028h Specify the device data for device number 20 Be careful not to corrupt the data for device number 21 Outpw 0x0000h 0x3000h Start cyclic communication...

Page 93: ...a change on this port an input change interrupt will be issued 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 This address also contains a change interrupt setting for parts of...

Page 94: ...7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 0 X X Read the current settings Start WORK Inpw 0x00C2h End Outpw 0x00C2h WORK WORK WORK and 0x9FFEh WORK WORK or 0x6001h Specify the mask and port data to monitor In t...

Page 95: ...ite back the data you just read in order to clear the change interrupt flag End Assume that the routine is started by an interrupt being issued _____ INT LOW Sts Inpw 0x0000h Read the status data in t...

Page 96: ...m 0x5300h or WORK Outpw 0x0004h Data Outpw 0x0000h Com Write back the data you just read in order to clear the change interrupt flag Note that the command is different from the one used to read the da...

Page 97: ...w Add Data Write back the data you just read in order to clear the change interrupt flag End Assume that the routine is started by an interrupt being issued INT LOW Sts Inpw 0x0000h Read the status da...

Page 98: ...pw 0x0004h Start Com 0x5100h or WORK Outpw 0x0004h Data Outpw 0x0000h Com Write back the data you just read in order to clear the change interrupt flag Note that the command is different from the one...

Page 99: ...IOPIB Port 3 Output Output value to the general purpose I O port IOPIB 1 When the whole address map can be used Start End Outpw 0x0108h 0x1200h Outpw 0x010Ah 0x5634h Write data to the I O device G9002...

Page 100: ...r and issue a write command In order to read port 0 on device number 2 and then read the I O buffer Discard the upper 8 bits Issue a read command to read port 0 on device number 5 and then read the I...

Page 101: ...the following order 1 Write the command to the PCL device register 2 Write the data lower 16 bits 3 Write the data upper 16 bits The writing order to the FIFO is specified for the PCL device in the us...

Page 102: ...PCL device that received this communication returns the specified register data to the center device The returned data is stored in the receiving FIFO When reading data while checking the RDBB Com In...

Page 103: ...tiplication rate 1 PRFH setting Process the next set of data the same way YES NO PRFL setting Write a register write command and place the data in the FIFO Lastly issue a device communication command...

Page 104: ...ce receives the data correctly the PCL device should start Check the EDTE bit to see if the device communication was successful or not Outpw 0x0006h 0x00B5h Outpw 0x0006h 0x00C7h Outpw 0x0006h 0x0000h...

Page 105: ...100h Outpw 0x0006h 0x0085h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0051h Send command data to the G9004A and it will process it one command at a time similar to a CPU to control the PCL6045B NO YES Dev...

Page 106: ...definitely started operation if there is no problem with the command data NO YES Sts 28h Inpw 0x01A0h Bit1 1 Outpw 0x0006h 0x0400h Outpw 0x0000h 0x4028h NO Dev Sts Inpw 0x0000h CEND 1 A End YES Write...

Page 107: ...is set to 1 or more the CPU emulation device will repeat multiple processes continuously In this case specify how to modify the addresses that will be output for each process 0X Address is fixed 10 I...

Page 108: ...n be stacked up for sending in the FIFO When a certain number of commands is stored in the FIFO send the command data to the CPU emulation device using data communication While interpreting the comman...

Page 109: ...terminal for a certain interval the local device will return a break frame If the center device receives this break frame it sets the BRKF bit in the status STSW register HIGH and changes the ____ INT...

Page 110: ...IGH 80 MHz 6 Does the data transfer speed match the setting on the center device 7 When the DNSM is HIGH is the address set properly through the ___ DN 5 0 terminal The address must be set using negat...

Page 111: ...ends of the cable 3 Is a terminal resistor connected in some other position not at the ends 4 Is the inductance of the pulse transformer too low 5 Is the pulse transformer connected properly 6 Are th...

Page 112: ...external noise into the LSI Hold the unused input terminals to 3 3 V or GND level Do not short circuit the outputs Protect the LSI from inductive pulses caused by electrical sources that generate lar...

Page 113: ...following conditions and do not reflow more than two times Temperature profile The temperature profile of an infrared reflow furnace must be within the range shown in the figure below The temperature...

Page 114: ...charge 2 Operators must wear wrist straps which are grounded through approximately 1M ohm of resistance 3 Use low voltage soldering devices and make sure the tips are grounded 4 Do not store or use L...

Page 115: ...or use in commercial apparatus office machines communication equipment measuring equipment and household appliances If you use it in any device that may require high quality and reliability or where f...

Page 116: ...is issued this bit turns 1 until the break communication is complete This bit stays 0 for all other conditions 2 2 Operation commands The following operation commands have been added Command Descript...

Page 117: ...s masked The status register is changed 1 MBRK By setting this bit to 1 the BRKF interrupt is masked The status register is changed 2 MIOP By setting this bit to 1 the IOPC interrupt is masked The sta...

Page 118: ...YN changes in units of 1 sec This is a read only register The center device always count the cycles and you can read the amount of time that has passed just before changing the MSYN The counter counts...

Page 119: ...tory Level shifter is not needed 1 SO 2 SOEH 3 _____ SOEL 4 SI 1 2 Function of I O port terminal When used in output mode these terminal outputs are open drains or ordinary output You can select eithe...

Page 120: ...Input terminals of G9002A can connect to 5V Therefore input voltage items are brought together and items of input voltage 5V I F is deleted 2 2 Recommended operating conditions There is difference as...

Page 121: ...G9002A Terminals except CLK SI and SOEI 0 8 CLK SI SOEI 0 6 High input vltage VIH G9002 Terminals except CLK 2 0 V CLK VDD 0 8 G9002A Terminals except CLK SI and SOEI 2 0 CLK SI SOEI 2 4 Hysteresis v...

Page 122: ...DA70131 1 3E VIII 4 3 External dimension There is difference as follows 1 80 HD D e A2 Amax A1 y L HE E G 9 0 0 2 A XXXXXXXXX J A P A N C b...

Page 123: ...12 1 11 9 12 12 1 D 11 9 12 12 1 11 9 12 12 1 Amax 1 6 1 7 A1 0 05 0 1 0 15 0 1 A2 1 35 1 4 1 45 1 4 b 0 18 0 22 0 27 0 13 0 27 e 0 5 0 5 C 0 1 0 145 0 2 0 09 0 2 y 0 08 0 08 L 0 45 0 75 0 3 0 75 HE...

Page 124: ...uding pins 14 4 14 0 4 Third Dec 21 2018 G9002A 1 Corrections in 4 1 List of terminals table on of II 3 and II 4 Option field of No 1 5 V added Option field of No 2 5 V added Option field of No 3 5 V...

Page 125: ...DA70131 1 3E www pulsemotor com group Information www pulsemotor com group support Issued in December 2018 Copyright 2018 Nippon Pulse Motor Co Ltd...

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