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Norsk Data NORD-100, Manual

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Summary of Contents for NORD-100

Page 1: ...NORD 100 Input Output System ...

Page 2: ...ent Norsk Data A S assumes no responsibility for the use or reliability of its software on equipment that is not furnished or supported by Norsk Data A S The information described in this document is protected by copyright It may not be photocopied reproduced or translated without the prior consent of Norsk Data A S Copyright 1980 by Norsk Data A S ND 06 016 01 ...

Page 3: ... 30 mm and 40 mm Use the order form below The manual may also be placed in a plastic cover B This cover is more suitable for manuals of less than 100 pages than for large manuals Plastic covers may also be ordered below 51 w A Ring Binder B Plastic Cover Please send your order to the local ND office or in Norway to Norsk Data A S Graphic Center PO Box 25 Bogerud 0621 Oslo 6 Norway ORDER FORM I wou...

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Page 5: ...PRINTING RECORD tinting Notes 12 80 NORD 100 INPUT OUTPUT SYSTEM Publication No ND06 016 01 Norsk Data A S Graphic Center D H D D D P O Box 25 Bogerud NorSk Data 0621 Oslo 6 Norway M M ...

Page 6: ...ould be replaced by the new one New versions and revisions are announced in the Customer Support Information CSI and can be ordered as described below The reader s comments form at the back of this manual can be used both to report errors in the manual and to give an evaluation of the manual Both detailed and general comments are welcome These forms and comments should be sent to Documentation Dep...

Page 7: ... Output system In the manuals covering specific device controllers a knowledge of these concepts is assumed Since this is a hardware manual it should be of interest to all technical and maintenance personnel who wish to gain a good under standing of the connection of I O interfaces to the NORD lOO computer system system software personnel who program I O interfaces They should read Section I PRERE...

Page 8: ...n Part I Section II describes the functions of the system bus the NORD 100 bus Section III describes using the NORD lOO bus in programmed information exchanged Section IV describes the separation of interrupting l O interfaces Section V covers how information is exchanged directly between the NORD lOO memory system and HG interfaces Section VI covers the NOR D 100 bus extender Related manuals cont...

Page 9: ...of the key words in the design of the NORD lOO computer system The basic difference from one installation to another is found in the memory size the software configuration and in the input output system i e the selection of peripheral equipment Therefore a flexible and modular design of the above mentioned modules is specially important in order to configure a system after a customer s wishes ND 0...

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Page 11: ... Configuration Examples I 2 7 PROGRAMMING OF I O DEVICE CONTROLLERS INTERFACES THE INPUT OUTPUT INSTRUCTIONS IOX IOXT I 3 1 General I 3 Introduction to IOX IOXT I 3 Format and Functions of the IOX and IOXT Instructions I 3 2 Definition of IOX IOXT Transfer Direction I 3 3 Calculation of the IOX IOXT Device Register Address 3 6 The Device Register Address Range 3 6 Specification of an I O Device Re...

Page 12: ...tification of an Interrupting I O Device Controller General The Ident Code The Ident Instruction The Ident Search Mechanism Input Output Interrupt Programming Initialization of the Interrupt System I O Interface Interrupt Generation Handling of I O Interface Interrupts THE NORD IOO BUS GENERAL THE NORD 100 BUS BUS REQUESTORS A NORD 100 BUS CYCLE GENERAL DESCRIPTION FUNCTIONS OF THE BUS CONTROL LOG...

Page 13: ... Instruction Entry Point Generation IN 2 1 IOX IOXT Microprogram Operation III 2 4 IOX IOXT Execution and the NORD IOO Bus III 2 7 IOX IOXT Execution and the HO Interfaces Ill 2 11 PIO Interface Module Organization III 2 12 Hardware Implementation of the Device Identification Logic Ill 2 15 IDENTIFICATION OF INTERRUPTING I O INTERFACES EXECUTION OF THE IDENT PLxx INSTRUCTION INTRODUCTION IV I I EX...

Page 14: ...ND THE NORD IOO BUS V 4 1 DMA TRANSFERS AND THE DMA CONTROLLERS V 5 1 NORD IOO BUS EXTENDER BEX GENERAL VI 1 1 FUNCTIONAL DESCRIPTION VI 2 1 Definition of Terms VI 2 1 Organization of Modules in a Bus Extended System VI 2 2 CONTROL OF THE BUS EXTENDER BEX MODULES VI 3 1 Introduction VI _3_1 The Memory Address Routing Mechanism VI _3_2 Hardware Switch Setting VI 3 4 Bus Extender BEX Programming Spe...

Page 15: ...INGS FOR THE DIFFERENT NORD 100 MODULES C 1 Switches on the CPU Module C 1 ALD Automatic Load Descriptor C 2 Console Speed setting for console terminal C 2 Switches on Floppy and 4 Terminals Module 3010 C 3 1 Floppy Disk System C 3 2 Terminal Group C 4 3 Initial Baud Rate for Terminals C 4 Switches on Memory Modules 3005 C 6 Switches on the 10MB Disk Module 3004 C 7 Switch Setting on the Pertec Ma...

Page 16: ... 5 xiv Page NORD lOO BUS BACKPLANE SIGNALS F 1 Representation of Signals in Timing Diagrams F 7 SCHEMATICS G 1 NORD lOO CPU G 2 4 Terminals and Floppy Disk G 7 8Terminals G 12 10MB Disk Controller G 17 Dynamic Ram G 19 ND 06 016 01 ...

Page 17: ...d users with special real time requirements running direct tasks may bypass the HO system for direct access to specific devices DEF N T ON OF TERMS As shown in Figure l 1 the I O system is part hardware and part software PROCESS user program SINTRAN lll OP SYSTEM i DEVICE DATA BUFFER l l l l DEVICE DEVICE DRIVER l CONTROL gingham A IT LER Device DEVICE DATA I FIELD I DEVICE REFERENCE TABLES DATA F...

Page 18: ...al such as a terminal or may be capable of driving several peripherals such as disk units For each device control er there is an entry in a device data field table A device data field defines a device and is used by a device driver the program that accesses and controls a peripheral For each device there is a device data buffer where information between the operating system and the I O system is e...

Page 19: ... MAN GFMENF l MODUI e TELEIYPE AUTOMATIC INVEHFACE WEST UH IENIIOR ICHECK CORREC DEVICE IN E FACE MODULE MEMORY MODULE DJ oT Flo uh _ DISPLAY I I PANEL T Figure 2 7 NORD 700 Bus Structure LJ DEVICES All communication between NORD 100 modules is provided by this bus except CPU MMS and Cache communication Therefore the NORD lOO bus is general purpose to allow all classes of NORD lOO modules simply t...

Page 20: ...ncerned However the difference between a 12 or 21 position system is easily visualized by the organization of the card crates and the size of the cabinets In the 12 position version the required power is supplied by a power supply located within the card crate refer to Figure 2 2 This approach leads to a very compact system z lll l I lllllllllllllllljIII III 1111 42mnm 1QGLKfl QfiCCC7YWCCI QQCCKZ YI...

Page 21: ...r part of the cabinet refer to Figures 2 3 and 1 2 4 Thus the cabinet must be bigger that the cabinet for a 12 position crate CONNECNON OFMODULE r DEPENDENT CABLES 420mm 2r4 A z I 1 r I NORDJOO zz BUSBACKPLANE ii 3 5 7 9 10 V3 WWW 510mm Figure 2 3 21 Position NORD 700 Crate Layout Front View ND 06 016 01 ...

Page 22: ...a 21 Position NORD 700 Backp ane System The NORD lOO bus backplane of either 12 or 21 positions is therefore firstly selected from the number of modules required in an actual system On the other hand physical dimensions in the cabinet and possible needs for future extension could also be taken into account ND 06 016 01 ...

Page 23: ...m of 8 crates The properties of the Bus Expander module are explained in Section VI Each NORD 100 bus backplane position contains a total of 96 lines power and ground lines included All positions in the backplane contain the same information i e they are equal This allows flexible configuration or reconfiguration of hardware The actual placement of different modules follow various rules which are ...

Page 24: ...System General As illustrated in Figure l 2 1 NORD 100 I O device controllers are connected directly to the NORD 100 bus This includes some important advantages The I O device controllers are connected to the same printed backplane as the CPU and the memory system no externalwiring increased realiability only one bus to connect between source and destination of a transfer makes a fast system l O d...

Page 25: ...ted l O device controller interface and the CPU A register This is illustrated in Figure l 2 3 NORD 100 BUS Y V L r 7 r AREG MMS DMA PIO MEMORY cpu CACHE CONTROtLER CONTROLLER MODULES Figure 2 3 FIG Data Exchange and Bus Usage The CPU is busy for every word byte to exchange The NORD 100 bus is allocated to carry data being exchanged Direct Memory A ccess IDMA High speed block oriented peripherals ...

Page 26: ...ore than one DMA controller interface may be activated at the same time thus sharing the DMA channels total band width ORGAN 2A T ON 0F NORD 700 MODULES All NORD lOO modules are made to a common standard Every module has at least one connector used for connection to the NORD lOO bus In addition a NORD lOO module may have one or two extra connectors carrying a total of 128 lines 64 lines in each co...

Page 27: ...eceive rs transm i tte rs 280 mm COMPONENT SIDE L 366 8 mm l Figure 2 5 Organization of an 0 Device Control er Modu e The standard part includes bus handshake control logic This part is standarized for all PIO device controllers all medium speed DMA controllers 10 Mb disk mag tape The device dependent part may handle up to four different PlO devices or one DMA controller A DMA controller may handl...

Page 28: ...ITEABLE CONTROL STORE I NORO 1oo BUS CPU CONSOLE RTc TERMINAL TTY OPERATOR PANEL OPTIONAL MMS fiDISPLAY 1 ______ _J CACHE up to 410M byte disk units 10M byte DISK H CONTROLLER L L you 1 4 Visual Dispiay Units DATA ENTRY H CONTROLLER vou 4 O Fioppy Disk 2 MEMORY MQDU LES I 128Kw Figure 2 6 NORD 700 Single Processor System ND 06 016 01 ...

Page 29: ...iguration shown in Figure 2 6 is given in Figure 2 7 IORD 100 CPU MODULE MMS 8 CACHE 10MB DISK CONTROLLER DATA ENTRY CONTROLLER POWER SUPPLY FREE l II POSITIONS I L MEMORY MODULES Figure 2 7 Configuration Example Physical Layout n Card Crate ND 06 016 01 ...

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Page 31: ... IOX IOXT In the NORD lOO instruction set there are two instructions usable for information exchange between the hardware device controllers and the CPU The mnemonics of the instructions are IOX and IOXT recognized by the MAC assembler NOTE IOX and IOXT are privileged instructions That is under a running system SINTRAN Ill running only privileged users may use IOX IOXT This is normally the device ...

Page 32: ...on a device assigns the exchanged information a special function Thus all classes of information may be exchanged data byte or word to or from FIG interface data registers not DMA inter faces transfer control information to HO and DMA interfaces control registers transfer status information from PIO and DMA interface status registers Instruction Formats All l O device registers are assigned an add...

Page 33: ...e CPU A register to a specified l O device register The actual transfer direction of the IOX and IOXT instructions is decoded from the device register address based on the following convention The transfer direction is input if the device register address is even That is bit 0 of the address is 0 The transfer direction is output if the device register is odd That is bit 0 of the address is 1 The p...

Page 34: ...er Illustration IOX Input l l l A REGlSTER l 5 1 l 10 9 1 0 1 IOX x x x _x 0 i 0 I even deVIce register I specified I O device register address bit 0 0 l l CPU l O SYSTEM IOXT nput CPU l 0 SYSTEM 1 r l A REGISTER 15 i o x x x 0 I T register even device register address Specified l O device register lOXT I Instruction register I CPU I l O SYSTEM ND 06 016 01 ...

Page 35: ...IOXT Output i 1 i i A REGISTER 15 14 1 o I 1 x x x x x 1 i 7 Odd device register address in T register Specified l O device register IOXT i instruction I CPU i O SYSTEM As indicated the lOX and IOXT instructions are general purpose 0 instructions The actual register on a device to access is specified in device register address The information to exchange and the transfer direction input or output ...

Page 36: ...ons which use the 16 bits T register to hold the device register address may hence theoretically address up to 64K registers addresses from 0 1777773 However the collection of all device registers implemented on interfaces designed at Norsk Data only cover the address area 0 17778 i e 1K register The remaining addresses which may be specified by the IOX or IOXT instructions are defined as describe...

Page 37: ...on IOXTAddress Range c c 1514 1312 11 1o 9 8 o I I i I l i I 1 1 I i C lxxx x I I I Addresses 7 I K 0 0 0 0 0 0 x i 1 NORSKDATA INTERFACES f 17778 20008 CUSTOMER 0 O 0 0 1 X F INTERFACES L 37778 0 o o 1 o x 40008 l _ __ 1 ILLEGAL 1 0 l 1 1 1 x 77777 x 8 SYSTEM 1000003 1 o o o o o 7 CONTROL REGSTERS 1007778 1 0 0 0 0 1 1010008 5 RESERVED 1 o o 1 1 1 1077778 1 O 1 0 0 0 110000 NORSKDATA 8 1 1 1 1 1 ...

Page 38: ...s area is not relevant to the HO system and are there fore not discussed any further in this manual Addresses from 7010003 7077775 are reserved by Norsk Data for future needs Addresses from 710000B 177777a are reserved by Norsk Data for future extention of the I O device register address range Since all present l O device controllers designed at Norsk Data may be specified in the address area 0 17...

Page 39: ...hen calculated by the formula dev reg addr dev no reg no Device Number Reg No V Registers O assigned one 2 1 0 interface lOX 38 to 17 I A 15 11 1o 9 V b lO 0 DEV NO REG NO The field REG NO may be from 2 to 4 bits depending on the g l numbers of registers assigned or lOXT g 1 the specified device I i l I I l l l l I 1514131211 10 9 l 0 0 O 0 0 0 O DEV NO REGNO Figure l 3 3 Device Register Address C...

Page 40: ...bers Appendix A Device Register Address range Device 3003 3078 Terminal 1 1 device number dev no 3003 300a 3078 is the device register address range 8 registers are assigned terminal 1 A There is always a unique correspondence between a peripheral the l O interface controlling the peripheral and a device number The device number corresponding to an l O interface is selectable by a thumb wheel on t...

Page 41: ...ed Programming specifications of some l O interfaces is given in Appendix B In order to understand the programming speicfications of an interface the organization and register assignment of Norsk Data produced interfaces is needed I 0 interface channels and registers An l O interface is said to have two channels if it can handle both input and output transfers simultaneously A one channel interfac...

Page 42: ...f A reg to specified control reg The Status Register The status register is a read only register IOX IOXT input By reading this register the status of an l O interface channel ready for transfer busy errors etc may be investigated LDT dev reg addr initiate T reg with dev reg addr of the status reg to access IOXT specified status reg A reg The Data Register The data registers is write only if it be...

Page 43: ...ister on line printer no 1 Solution The dev reg addr is calculated form dev reg addr dev no reg no The device number dev no should select line printer no 1 In Appendix A that is found to be 4308 The register number should point out the data register on the line printer interface The register number of the data register is found in the programming specifications of line printer interface Appendix B...

Page 44: ...N0 4348 38 4378 Program SAA 7 A 78 IOX 437 A reg dev reg 437a or LDT ADDR initiateTreg with dev reg addr SAA 7 A 78 IOXT Areg evel reg 437a ADDR 437 Example 2 Terminal Interface A terminal interface has two channels input from keyboard and output to terminal display Each channel is controlled independently and contains its own set of control status and data registers Input channel Register Registe...

Page 45: ... of input output channel Problem 1 What is the lOX lOXT device register address for the output channel status register on terminal no 1 Solution From Appendix A terminal no 1 is found to have device number dev no equal to 3003 In Appendix B programming specifications for a terminal interface the register number reg no for output channel status register is 68 Using the formula Dev reg addr dev no r...

Page 46: ...315 Correct Program Using IOX Convert to IOXT privately INPUT IOX 300 read input data form terminal 1 STA BUFF store A reg in BUFF OUTPUT LDA BUFF initiateA reg IOX 315 write data to terminal 2 BUFF 0 DMA INTERFA CE REGISTERS ACCESSIBLE BY IOX IOXT A DMA controller usually contains from 8 to 16 registers accessible by IOX IOXT instrucitons The IOX IOXT device register address is just as for PlO in...

Page 47: ... designer of each device controller However on Norsk Data designed interfaces both the functions and the formats of these registers have been standarized The format of the data register follows the format accepted by the external device for example ASCII to and from terminals Format and Functions of the Status Register The information available in an l O interface channels status register is set b...

Page 48: ...nal mode of device Bit 13 Operational mode of device Bit 14 Operational mode of device Blt 15 Operational mode of device Bit 0 2 The status register bits 0 2 are direct feedback of the corresponding bits in the control register of the same l O interface channel see control register format Bit 3 Device Ready for Transfer Status register bit 3 set or not set tells whether an l O interface channel is...

Page 49: ...MA transfer completed Bit 3 equal to 0 DMA transfer is going on Bit 4 Inclusive OR of Errors Bit 4 set to one an error has occurred in the l O interface channel investi gated More about the error is given in status register bits 5 15 actual bits are described in the programming specifications Bit 5 15 Nondefined Status register bits 5 15 are assigned by the I O interface designer and given in the ...

Page 50: ...ual both for the input and output channel of a device Format of the Control Register Format of A Register before IOX Load Control Register 1514131211109876543210 c r A V 1 Device dependent format Standarized on ND found in device s produced PlO and programming specifications DM A inte rfaces Bit 0 Enable interrupt on device ready for transfer Bit 1 Enable interrupt on errors Bit 2 Activate device ...

Page 51: ...ister Bit 1 Enable Interrupt of Errors Bit 1 set to 1 in an l O interface channel enables for interrupt on errors in the channel Control register 1x lNTERRUPT 15 3 ERROR Status register Bit 2 Activate Device The control register bit 2 set to 1 on an interface will in the input channel enable reception of incoming data from external devices in the output channel start output of the content in outpu...

Page 52: ...loop output data back as input data in off line testing of an interface Bit 4 Device Clear The control register loaded with bit 4 1 generates a reset pulse on the accessed l O interface The reset pulse will clear all bits set in both the control and the status registers The device clear bit is usually implemented only in the input channel control register of a device However the bit resets both ch...

Page 53: ...urse uses method 2 However in the following description and programming examples method 1 will be used Use and programming examples with interrupt is given in the section The I O System and the Interrupt System Programmed Input from a PIO Interface Reading a byte or word from a FIG interface may be divided up into three steps 1 Enable the input channel for reception of incoming data 2 Check whethe...

Page 54: ...CR READ INPUT CHANNEL STATUS REGISTER ISR A REGISTER INPUT DATA READY lSR BIT3 1 READ INPUT CHANNEL DATA REG C9 DR A REGISTER ND 06 016 01 ICR Input channel control register ISR Input channel status register IDR Input channel data register ...

Page 55: ...ccess Dev reg addr Dev no ICR no Dev reg addr Dev no ISR no Dev reg addr Dev no IDR no device no terminal no 1 dev reg addr for input control reg 303 dev reg addr for input status reg 302 dev reg addr for input data reg 300 set bit 2 in A reg A reg ICR ISR A reg ls ISR bit 3 set No i e not ready Yes i e ready read data store data in BUFF return If the program above should be entered for execution ...

Page 56: ...a register 3 Initiate the output transfer by activating the output channel This sequence applicable for output to all Norsk Data produced PIO interfaces is illustrated in the flow chart below I READ OUTPUT CH STATUS REGISTER OSR A REGISTER OUTPUT DATA REGISTER READY OSR BIT 3 1 NO OSR OUTPUT CHANNEL STATUS REGISTER ODR20UTPUT CHANNEL OUTPUT DATA DATA REGISTER TA REGISTER ODR OCR20UTPUT CHANNEL CON...

Page 57: ...rface to access 08R 2 DEVNO OSR no address of OSR ODR DEVNO ODR no address of ODR OCR DEVNO OCR no 0 o address of OCR OUTPUT IOX OSR read status BSKP ONE 30 DA Ready JMP 2 NO LDA BUFF Yes initiateA register lOX ODR A reg ODR SAA 4 InitiateA reg control IOX OCR A OCR JMP OUTPUT Jump return ND 06 01 6 01 ...

Page 58: ...MA interface what to do The transfer parameters are written into physical device registers located on the controllers Typical transfer parameters and registers are Memory Address Register MAR holds the first memory address to read from DMA output or write into DMA input Block Address Register BAR holds the first address to read DMA input from or write DMA output to on the physical device Word Coun...

Page 59: ...ination and Status Check The DMA transfer is completed when the word counter is zero On the DMA controller status register bit 3 ready for transfer is turned on If the interrupt system is on ION and interrupt is enabled on the controller this causes interrupt on level 11 If the interrupt system is not on a complete transfer is found by polling continuous reading on status register bit 3 More about...

Page 60: ...l word regieter 3 DMA TRANSFER V READ DEVICE Device data interface Memory WRITE DEVICE Memory MAR Interface Device MAR 1 MAR V we L1 wc STEP 2 NO wc 0 L YES DMA TR ANSFER QUALITY CHECK FINISHED STATUS REGISTER A STEP3 MAR end A MAR _ MAR 0K and start WC start YES Figure 3 7 DMA Transfer in Three Steps Initiate next transfer ND 06 016 01 ...

Page 61: ...IOQ AR DISK ADDRESS MEMORY AREA TO BE EXCHANGED IOX WC DISK N0 0F WORDS IOX CR I CONTROL REGISTER W Q START TRANSF SELE T UNIT IN DISK SYSTEM MODE OF OPERATION READ I I I I I I I I I I I I I I I I I I I I I I I I I I Figure I 3 2 DMA Initialization Illustration Disk ND 06 016 01 ...

Page 62: ...S DRESS I I MEMORY ADDRESSISINCREASED BY ONE I I I I I DATA DIRECT I DATA FIFO DATA TO MEMORY MEMORY _ BUFFER AREA TO BE EXCHANGED NO OF WORDS WORD HAS BEEN EXCHANGED I I I I I I I NO OF WORDS TO EXCHANGE S I DECREASED BY ONE WHEN ONE I N I I I I I Figure 3 3 DMA Transfer ustrat on Disk ND 06 016 01 ...

Page 63: ...MEMORY ADDRESS Ex NO OF WORDS ZERO CONTROL REGISTER m 0 3 L AND HNTERRUPT CPU To LEVEL 11 l STATUS REGISTER RET l PHYSICAL CONDITIONS A l I wcz I l wcz WORD COUNTER ZERO RFT READY FOR TRANSFER __ __ _ _ ___ __ ___ ______ Figure 3 4 DMA Transfer Comp eted Disk ND 06 016 01 ...

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Page 65: ...tually caused an interrupt is found by reading the status register of the interrupting channel on the interrupting device 1 End of operation interrupt occurs if a device is ready for transfer status bit 3 1 and control register bitO 1 This means for a PlO interface in the output channel data has been transmitted next character to output may be loaded to the output data register input channel input...

Page 66: ...ently running is activated or if the current program level gives up its priority The level change is a micro programmed procedure which purpose is to establish the interrupting level as the new currently running PL while the previous PL is put into a waiting state To ensure fast level changing context switching each of the 16 program levels have their own set of registers and status indicators loc...

Page 67: ... 3 555 ll 39 3 50 95 it an ANN IAIN 1 65 E985 539 30 EEmoi goo 625 Qnmcm 53 85 625 89mm 52 25 320 m zo E9m m 33 95 25 San mESE 83 520 s 3 53m EEOC 3n 1 vi GE DE 20_ Hmo 68 33 32 35555 Figure 4 7 External Interrupt System ND 06 016 01 ...

Page 68: ...sition in PIE Example 7 LDA 76033 76033 A TRR PIE A PIE 1514 131211109876543210 0111110000011011PIE Interrupt is enabled on the levels 0 1 3 4 10 11 12 13 14 All other levels are disabled Level 14 requires speical attention refer to the following description Each bit position set in the PID register corresponds to an active program level The current running level is given by the highest correspond...

Page 69: ...m counter SP on the current level 3 The PL program level register is copied into the PVL previous program level register 4 The PK new level priority code register is copied into the PL program level register The CPU has at this moment changed level 5 The SP saved program counter on the new level is copied to the CP current program counter 6 A fetch is issued i e the first machince instruction on t...

Page 70: ...ftware i e interrupt on these levels has to be programmed by means of TRR PID MST PID instructions Interrupt on the levels 10 to 15 may be set either by program or by hardware Each of the levels 10 13 and 15 are assigned a unique interrupt line in the NORD 1OO bus which may be activated from any slot position Level 15 is not used by Norsk Data equipment but may be used by users requiring immediate...

Page 71: ...hese lines have been standarized Level 10 is used by the output channel of all PIO interfaces Level 11 is used by all DMA controllers Level 12 is used by the input channel of all PIO interfaces Level 13 is used by the real time clockls and FIG devices which need special attention Level 15 is not used by Norsk Data produced hardware or software but is available for special purposes needing immediat...

Page 72: ...I I I I 1 Enabled LeveI Detection I 4 select IeveI with the PRIORITY ENCODER highest priority I I I I _ _ _ I I I D LeverwzthIhIghesI prIorIty I r I t L CURRENT LEVEL COMPARE I I I I Is I I I I I l DIFF _ INTERRUPT Register select bits PLO 3 I 1 Internal Interrupt LEVEL 14 NO CONNECT error IOX timeo ut is one source Figure 4 3 NORD 700 External Interrupt Handling ND 06 016 01 EXTERNAL INTERRUPTS ...

Page 73: ...ll devices the l O interface causing the interrupt is unknown That is the device number is unknown and the lOX device register address is not possible to define Therefore a device interrupt identification is needed The Ident Code Each l O device controller is assigned an interrupt vector referred to as ldent code id code The ident code related to Norsk Data produced interfaces has been standarized...

Page 74: ...instruction IDENT PL 12 will only search for interfaces driving interrupt line level 12 BlNT12 A possible existing interrupt on level 10 or 11 is ignored and handled later by IDENT PL 10 and IDENT PL 11 respectively The ident code which is unique for each device is used to via an ident code table to enter the interrupting device s data field The data field contains an address pointer to the device...

Page 75: ... which stopped the search is returned to the A register NOTE In step three the interrupt is removed from interface by resetting of the interrupt enable bit i e bit 0 or 1 in the channel s control register That is an interface channel should be reenabled after being served by the ident instruction The search mechanism used by the ident instruction includes some important notes Note 1 There should n...

Page 76: ...counters on the levels to be used must be initial ized i e they must all point to the program to be executed on the different levels if the 2 error indicator is enabled for interrupt iiE bit number 5 care should be taken that this indicator is cleared in the status register bit number 3 for all levels being initialized The NC internal interrupt Code register the PES Parity Error Status register an...

Page 77: ...EMLI_ Output Data Reg AND TBEMT output data reg is empty HFT ready for transfer bit 3 in output status register status register INTEN interrupt enable bit 0 in control register IN INTERFACE 10 PIE Bit 1o 1 El PID REGISTER IN CPU DO NOTHING DO NOTHING DECODED BY HARD WARE INITIATE MICRO PROG LEVEL CHANGE SAVE INTERR REQUEST WAIT UNTIL PL 10 ND 06 016 01 ...

Page 78: ...bit 3 In status I I INTEN I o 1 I I 2 I I I I I I CONTROL REGISTER I I o I BINT11 I I RFT I 4115 2 I AND l I I I I STATUS REGISTER I I I I I I I I I I register I I IN INTERFACE I I I I I I I V j Y SAVE INT REQ 84 WAIT UNTIL PL 11 JC DO NOTHING DO NOTHING INITIATE LEVEL CHANGE NDOS 016 01 IN CPU HARDWARE DECODED ...

Page 79: ...OO 8T5 INTEN I Input Control Register I l I I l l I I l I I BINT12 RFT l i QA INPUT DATA I REGISTER I AND _ I I l I I I I DA Data AvaIlabIe I I RFT Ready for transfemah 3 in status register I I INTEN Internai enable I I Pl Current running level I i BINTIZ Interruot request level 12 I IN INTERFACE I I l I l I l l iv I V IN CPU DECODED BY HARDWARE ...

Page 80: ...ould be followed Execute IDENT PL to identily the inlerrupt source Use DENT code 10 separate l O drivers I Use IDENT CODE in A register to separate device drivers r l O DRIVER 1 Check INTERRUPT REASON by reading STATUS REG 7 NO Y l ES JUMP ERROR READ DATAor OUTPUT DATA ROUT N Enable and Activate devnca for next transfer L L I l l l O DRIVERZ I ND 06 016 01 ...

Page 81: ...I 4 17 8 60 mEExw 82 8 0 2 365 4w w4 HmDmmm PZ Dmo Oh smFXm xO Efmoi 53 0 Duo 2 Em Sun 832 9 33 35 32 2 8 52 mQOo kZmo xx _n_ _ Zw0_ xx m_ xx 22 5 6 I a o fl nwm mlma wlflop Z I E E NDOG 016 01 ...

Page 82: ...H DRIVER n JMP FINISH FINISH WAIT JMP LEV xx O o o o o read ident code modify program counter with the ident code report the error read status register is interrupt reason error Yes bit4 dev error 1 No serve the ready for transfer condition jump to routine for giving up priority give up priority entry point to LEVxx after WAIT More about the hardware involved in the I O interrupt system is describ...

Page 83: ... A l i t4 NORD iOO MEMORY l O DEVICE MEMORY CENTRAL 7 MANAGEMENT CONTROLLER MODULES PROCESSOR CACHE e4 Kw module Figure ll 7 The NORD 700 Bus The NORD lOO CPU uses the bus for memory transfers to and from the memory system and for I O transfers to and from its connected peripherals In addition some NORD lOO bus peripherals DMA controllers can initiate trans fers directly to and from the memory sys...

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Page 85: ...n addition refresh of the NORD 100 memory system requires access to the NORD 100 bus As a common resource the NORD 100 bus has to be allocated before it may be used Once allocated the bus is busy to other activities while the granted bus user may transfer one word As the transfer is completed the NORD 100 bus should be released for next eventually requesting bus user ND 06 016 01 ...

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Page 87: ... is called release TIME TRANSFER ALLOCATION RELEASE V ONE BUS CYCLE Figure 3 7 A NORD 700 Bus Cycle Refer to the illustration Figure l 3 1 A NOR D 100 bus cycle consists of three main events allocation of a requesting bus user transfer one word termination and release of the bus The allocation is handled by a Bus Control Unit BCU physically implemented on the CPU module That is the BCU decides whi...

Page 88: ......

Page 89: ...re operating completely asynchronously That is the bus allocation requests may be passed to the BCU completely asynchronously even simultaneously causing competition Conflicts are avoided by the BCU through a priority allocation arbiter Based on a priority allocation algorithm and the present active bus allocation requests one requestor is selected for the next bus cycle while possible other activ...

Page 90: ... not located on the CPU or MMS module for example Error Correction Control Register on the memory modules TRR ECCR If any of the six above mentioned operations are in progress the CPU micro program activates the signal BUSRO CPU bus request input to the CPU alloca tion arbiter In addition to the signal BUSRO passed to the BCU the microprogram informs the CPU bus handshake logic which transfer that...

Page 91: ... to select only one DMA controller as granted bus user at the time the DMA request acknowledge signal is daisy chained in the NORD lOO bus backplane The daisy chain then establishes a sequential priority scheme between DMA controllers Physical implementation of the daisy chain is described in later sections Memory Refresh Allocation Request Refresh is a periodical operation needed by the dynamic M...

Page 92: ... arbiter controls the access to the NORD lOO bus based on the following rules Already allocated bus is not interruptable The bus cycle going on is aborted if it exceeds a time limit of 8 p s If the bus is idle and an allocation request appears alone the rule is first come first served Since all the request signals appear asynchronously conflicts between simul taneous requests may happen In such ca...

Page 93: ...does not try to allocate the NOR D 100 bus 2 CPU tries to allocate the bus but has to wait for another bus activity 3 The bus is allocated to the CPU 4 CPU has finished its bus cycle and releases the bus Example 7 CPU requests the NORD lOO bus first after previous allocation is released H 2315 15 6 us 10mb disk _ llllllllllllllllllllll 550m j r _ i llllllllll I T k depends on N I CPU actIVIty I pr...

Page 94: ...o exchange or for one memory refresh cycle One bus cycle should not last for more than 8 p s This is monitored by the BCU At the time of allocation the BCU starts a timer This timer is reset by a handshake mechanism between granted bus user and its accessed device signifying transfer completed The transfer completion signal is named BDRY Bus Data ReadY and will be explained in proper context later...

Page 95: ...ESET TIMER BDRY bus cycle completed from I memory or 1 0 system Reference to cache 8 us I or shadow memory I TIMEOUT I I ABORT CYCLE RELEASE BUS MEMORY ACCESS E D I I I I l I I HARDWARE DECO 1 MOR Memory out of range 2 IOX I O execute error No response from accessed I O device controIler UNPREDICTABLE NOISE 1 POW MOR PTY IOX ffiA INTERNAL INTERRUPT DETECT REGISTER LEVEL 14 I I I I I I Figure ll 4 2...

Page 96: ......

Page 97: ...lthough the granted bus user may either be the CPU a DMA controller or memory refresh only CPU and DMA cycles include any data exchange Therefore granted bus user when talking about data transfers is either the CPU or 3 DMA controller ORGAN 2A T ON OFA NORD 700 BUS CYCLE Due to the multiplexing of addresses and data on the same physical bus lines one NORD lOO bus cycle may be divided up into two s...

Page 98: ...ata is exchanged between the I O register or memory location specified in the address cycle By contrast of the address cycle the data cycle includes an asynchronous handshake between granted bus user and accessed device The handshake is initiated by the granted bus user issuing a control signal indicating start of data cycle Termination and release of the bus cycle is done by the accessed device a...

Page 99: ...he IOX and IOXT instructions Both these instructions exchange information between the CPU A register and a specified I O interface register Other sections in this manual have covered how and when to use the IOX IOXT instructions in programmed control of PIO and DMA interfaces Thus this section is intended to give a description of how these instruction are executed That is how they are handled by t...

Page 100: ......

Page 101: ...ion to the microprogram is covered by the manual NORD lOO Function Description and is not repeated here However some remarks relevant to the IOX and IOXT as privileged instructions are given IOX and IOXT are privileged instructions If MMS is on privileged instructions may only be executed by programs executing with a ring priority greater or equal to two RING 2 2 That is IOX IOXT and other privile...

Page 102: ... to the CPU as described below Figure ll 2 1l PRlV INSTR lS LEGAL Bc14 EPRIV 1 PRlV lNSTR NOT LEGAL BC14 EPRlV o EPRlV Enable privileged instruction 8014 B connector line carrying EPRIV from MMS Memory Manage ment System to CPU Figure Ill 2 7 NDOB 016 01 ...

Page 103: ...cmE 29 22 2 2 55 m 55 8mg 5363 9 6 0 309 22950 5 0 5 2 222 205 30 53 52 llllll l Y z 36 mo 8 87302 m O UBHJUWXQ an o 25 m NEG 1 lllll 8 9 Eu _ o m _ 522002 020 5 _ ET 55 8 52 3 is guano TEES _ r5255 2255 o _ u l u an 20 52 52 _ m 83 29 mmmmoo J A 30m Ax 05 2 _ muUZmDOmm _ 2 moOm _ races 4 _ l I 2025 _ A l l 8 n o 8 FSZ SEQ _ Owl_ _ OZ Ibwz_ _mn_ Hm_ _ nEma EEO ND06 016 01 ...

Page 104: ...ISTER GPR 0 10 DRl lOXXT COMMON ROUTINE FOR EXECUTION OF lOX lOXT The functions of the common routine lOXXT is of course to exchange infor mation between CPU A register and a specified l O interface register The l O register to be used specified in the device register address normally has to be accessed via the NOR D lOO bus The only exceptions are access to terminal number 1 and the Real Time Clo...

Page 105: ...dshake logic during lOX lOXT execution When a NORD lOO bus cycle is needed the microprogram requests allocation of the NORD lOO bus In addition the microprogram informs the CPU bus handshake logic which cycle lOX IDENT or memory reference it should handle In case of IOX the device register address to be used in the lOX address cycle is enabled onto the internal CPU bus lDB Refer to Figure ll 2 3 a...

Page 106: ...CPU ALLOCATION ACKNOWLEGDE iACT INI ORM CPU BUS j START CYCLE _ o CYCLE _ HANDSHAKE LOCIG IN PROGRESS PASS DEv REG ADDR 2 l TO IDB A R Y DD Essc CLE BAPR RELEASE WAIT ADDRESS CYCLE l COMPLETED 1 IS ADDRESS CYCLE WA T I FINISHED 1 DATA CYCLE l BIOXE C UTPUT OR i INPUT HAND mm A 4 REGISTER TO 108 SHAKE BiNACK RELEASE WAIT DATA CYCLE l BURY COMPLETED L DATA i CYCLE COMPLETED WA T I CPU BUS l HANDSHAK...

Page 107: ...U As other bus cycles the lOX IOXT cycle is handled by the bus handshake logic as an address cycle and a data cycle In the address cycle all I O interfaces simultaneously are presented the device register address Based on this address one l O device register is selected to communicate with the CPU during the data cycle As indicated in the previous section the microprogram is independent of the lOX...

Page 108: ...us handshake logic holds the addresses albout 50 ns after leading edge of BAPFlO before it continues with the data cycle The microprogram now moves the A register via IDB to WDA The bus hand shake logic passes WDA to the BD lines When the data the A register is valid on the BD lines the handshake logic activates the signal BlOXEo Upon receiving BIOXE active all I O interfaces look at the device re...

Page 109: ...tion actually is The IOX IOXT transfer direction is selected by the HO interface that finds equal after the reception of BIOXE If the accessed interface finds that the specified l O register to be exchanged is an input register the interface activates the signal BlNPUTo The bus handshake logic reacts on the active BINPUT0 signal by closing the output from the WDA buffer and then activating the sig...

Page 110: ...2 o3 mmmmoo o3 20 sfl Ll Ewell H Q _ Dn_z_ _ _ _ _ _ _ V V egg 1 35 28 586 56 a LA 0 54 25 20 mo wwE wm mmz 0m V otiza Sm m 5 8m awmmmoo A o amtl o t1moil 58 w40 o P o Om AI 0 AT mo 5 004 ma m U o wmm moo _ _ _ _ _ u _ _ _ _ _ _ 7 cs 00 1d wa mmo om mm D ND 06 016 01 ...

Page 111: ...ndent of the peripheral connected to the interface This implies that all peripherals appear equal to the NORD lOO bus and could be handled equally by the CPU bus handshake logic On a FIG interface module the bus control logic is standarized to handle up to four different devices accessed to the NORD lOO bus Refer to Figure l 2 6 EXTERNAL NORD lOO CABLING TO DEVlCE BUS COMMUNICATION A fl r 1 A B DEV...

Page 112: ...faces The description of an l O interface bus control logic is therefore applicable to both PIO and DMA interfaces The main function of the I O interface s bus control logic is to handle the hand shake with the CPU bus handshake logic during IOX IOXT execution The address and data flow and the associated control signals invovled in this handshake have already been described in timing diagrams Thus...

Page 113: ...UAL OTHING I CPU BUS YES START o CYCLE HANDS HAKE I LOGIC DECODE SELECT I DEVICE REGISTER I I B NPUT YES INPUT I REGISTER I BINPUT __ ___ ACKNOW l WAIT FOR LEDGE I BINACK J I I I BINACK INPUT REG 80 TO I TO 30 j OUTPUT REG DATA I DATA TRANSFER I I BDHYL ACCEPTED COMPLETED I VALID I RELEASE BUS J 1 ________ I I SELECTED J SELECTED A REGISTER INPUT REG OUTPUT REG 4 DATA ON 80 5 L j Figure 2 7 CPU Bu...

Page 114: ...ber The l O interface that finds device equal starts an IOX cycle on the interface Other interfaces do nothing The device equal interface starts the IOX cycle by decoding the register number bits in the device register address This decoding selects one of the registers on the interface to be accessed If the device register to be accessed is an output register the content of the 80 lines i e the A ...

Page 115: ...ual device number selected on an interface depends on the selected PROM location A PROM location is selected by a PROM address which is set by a thumbwheel Thus the device number of an interface is easily changed by turning the thumb wheel On l O modules controlling more than one peripheral type with different device numbers one seperate PROM thumbwheel and comparator is available for each periphe...

Page 116: ...s decoding may be performed either sentralized or in the device dependent part on single peripheral or multiperipheral controllers respectively The decoding is performed physically by a 3 to 8 line decoder A given bit combination input to the decoder gives one output line active That is the number specified in the register number field gives one line active which points out the register that is to...

Page 117: ...J F _ DEV CE NUMBER TREG NO x 1 OK REGISTER q___ CLOCK ENABLE NUMBER _ _ SIGNAL TO 2222 DECODER SELECTED 5 REGISTER V L é o DEV NO QM COMPARE FOR EOUAL DEVICE NUMBER DEVICE EOUAL THUMBWH DEV CE ENABLE DECODING FOR NUMBER CV NO PROM OF REG NO 0 PROM INTERF SELECT ON ADDR DEV NO OK ENABLE BIOXE__ COMPARE Figure 2 9 Device Identification Logic on a Sing e Device 0 Interface DMA Contro lers ND 06 016 ...

Page 118: ...o ESE _ 38 33 5 _4 moSmc 4 30m _ 0 51111111131413 E _ 5 28 ERR _ 02 3 xo _ _r _ _ A _ _ 556 _ m Bkomm OF H mmooowo N V Na W v 0 _ 2205 o _ oz 556 53mm m _ 332E530 556 020 r 02 mo v _ moo 8 8 _ _ o 9 E m _ _ Emma _ _ 23 5 50 2255 ofim 2 z m _ Z _ 23 s 8 50 2055 5 3 _ E 2325 a 2 333 mwmzoofifig i_ So 535 mdm mDm 2 10 02 Figure 2 70 Device Identification Logic 0n Mu ti Device 0 interfaces iP O nterfaces...

Page 119: ...rom other parts of this manual The need for and the function of the IDENT PLxx instruction has also been described Its purpose is to search for an existing interrupt on a specified level PLxx and return the ident code from the first found device with interrupt on specified level to the CPU A register This section is intended to give a more detailed description of how the IDENT PLxx instruction is ...

Page 120: ......

Page 121: ...cessfully entered IDENT M CROPROGRAM OPERA T ON The search for interrupts that is performed during lDENT PLxx execution is normally done in the NORD lOO bus However as for the IOX IOXT instruction there are exceptions Terminal number 1 device no 2 3008 is physically implemented on the CPU module Thus interrupts level 10 or 12 from this terminal are not detected by searching in the NORD 100 bus The...

Page 122: ...for interrupt has to be performed in the NORD lOO bus The microroutine designed to handle the IDENT PLxx search on the NORD lOO bus is principally equal to the lOX IOXT Bus Transfer routine The only difference is that in IDENT execution the microprogram tells the CPU bus handshake control logic to perform an interrupt search instead of an IOX IOXT information ex change Thus the interaction between...

Page 123: ...DRESS CYCLE I COMPLETED Is 1 ADDRESS CYCLE WAIT I FINISHED l DATA CYCLE l BOUTIDENT WAIT FOR y BDRV l A REGISTER TO BDRY RECEIVED l IDB Le IDENT RE CODE FROM I LEASE WA T INTERRUPTING BURY DEVICE IS I DATA CYCL VAUD ON ED I BD DBR COMPLETED WA l l CONTENT OF DBR TO A REG ADDRCYCLE PLXX IDB 0 15 3 80 0 23 DATA CYCLE IDENTCODE A D B A R Figure V 2 2 IDENTM cro Routine and CPU Bus Handshake Log c nte...

Page 124: ...he DBR register The microprogram moves DBR to the CPU A register and initiates the next machine instruction IDENT PLxx EXECUTION AND THE NORD 700 BUS This section is intended to give a description of how the DENT PLxx instruction appears to the NORD lOO bus This includes the operation of the CPU bus control logic and the control signals involved during DENT execution Background for signal response...

Page 125: ...t Search via the NORD 700 Bus am 20 o3 l_ mooon _ QZDOu m 4m w4 w m ZO m0 ummhz_ o mom Q_ _ XXJE oFZmOERJOm _ AI 28 25 _ _ _ IIIJ me so om _ o m0m 0 ZOFaEUmm wI k _ m40 0 Iom mm w40 o P D Om A 95 mm T XXJm m30 0 mmwmoo V ml l XX PZE mTO mo 11V 1 SEE in uu IIII ND 06 016 01 ...

Page 126: ...in position n This is illustrated in Figure IV 2 4 The search signal is called BINIDENT when it is input to a module and BOUTIDENT when it is leaving a module If the BINIDENT signal reaches a module with the flag interrupt on specified level set the search is stopped The interface that stopped the search returns its ident code to the CPU combined with BDRYO Modules with no interrupt flag set shoul...

Page 127: ... mnDO z H m mFOZ 4w m4 mZO Z_IC _ _mO_mn_ HmOE 9 Duo 5 2 rmmzd wz Dmo 4m mJDDOE HN wPOZ Z_ IU Iva mm HZmQFDOmPZmEZE t wmm mZO_ _ _wOa POVG E_ _w n kZ mofmmiz 0 653002 052 65 a 225 20 mooon ESE Emoinom 53 25 IIIIII oz 35 53 58 53 25 Ema 50m 20 5 mm 5 Na 8 I 1 mm 8 m 8 Eco mm 5 7 A 4 m COTOCOZ ND 06 016 01 ...

Page 128: ...EVICElSl ____ __ PLxx ON BD 6 _ ___ _ __ l _____ V 6 Y 1 v 1 Lxx VALID ON 30 BARRn l l l h PLxx LATCH l i l J L _ _ T V V WAlTTO START i SEARCH TON 100 ns NTERRUP I I AFTER BAPR SET ON LEVEL CONNECT l 0 I BlNlDENT TO I BOUTIDENT i I _____ I SET FLAG AND 1 DELAY lN l WAIT FOR I IIOTHER I BINlDENT __ BOUT lDENT IMODULESJI l BINIDENT l STOP SEARCH AND ENABLE lDENT CODE l RETURN IDENT TOBD COOE IDENTC...

Page 129: ...7 are used as illustrations to the text in this section Figure V 2 6 illustrates the IDENT control logic on a single device controller interface DMA controllers Figure V 2 7 illustrates how it is implemented on multi device interfaces several PIO controllers on one module The implementation is principally and functionally equal for both single and multi device controllers One may look at one part ...

Page 130: ...xed thumbwheel outputs That is a new PROM location containing the interface s ident code is accessed and enabled on to the NORDJIOO bus BD lines After an appropriate set up time BDRYO is generated to signify presence of valid IDENT CODE on the BD lines Now refer to Figure V 2 7 As indicated the multi device interface is an extended single device interface Each device A B has its own device number ...

Page 131: ...LXX I Q INTERRUPT ON LEVEL AND I s _ STOP IDENT INTERRUPT 0 5 PLxx ON LEVEL Q 3 CHECK N a I 14 TO o DEVICE THUMB_ IDENTIFICATION WHEEL DEV CE LOGIC h é__D R PROM IDENT T D v B IDENT CODE OUTPUT Q u FROM DEV NO PROM F PROM ADDR TH_ WHEELHDENT k F INVERT AND IDENT BINIDENT STOPIDENT OR _ Ca 22 BWIDENT BOUTIDENT Figure V 2 6 IDENT Contro Logic Implemented on Sing e Device Contro ers DMA Controllers N...

Page 132: ...____ _ _ v 85 _ v 85 V _ 22 SR 20 _ 3 20 _ Nuthwwpzwoflohm EDEEE _ 3 55 _ n q dazimm ll _ Ewo_ wo lu 11 _ mwmm wz 4 n _ _ u _ _ N m _ Ecoofi CEoEn n E3535 moSmo _ _ u _ 205 _ n _ 0 o m oz mo _ _ L q r _ _ _ ozs oz oz oz _ rcILIII _ rillxuéufi p _ T lllll LL d3 20 Hz m H _ u 3 2052 21 1 1 7 K _ O O m I _ WEE 2 E_ 2 xx v 0 AllE m _ HIIHIH TIIII IIIH J r O m O llllllllll _ 0 39 mo_ wo _ _ 20 325 _ _ haz...

Page 133: ...e by means of lOX IOXT instruc tions The functions of the program handling a DMA controller varies from one device to another and is not discussed here A general description is given in Sec tions 3 5 and l 3 7 l What is to be discussed here is the event of one word of information being exchanged directly between memory and a DMA controller Such a transfer is based on a defined handshake mechanism ...

Page 134: ......

Page 135: ...NORD 100 bus is needed for the exchange Therefore if any of the two above conditions occur on a DMA controller the controller will request allocation of the NORD lOO bus The bus allocation request from a DMA controller is referred to as a DMA request The DMA request named BREQ Bus REOuest is a line in the NORD lOO bus input to the Bus Control Unit BCU priority arbiter BREO is a shared wired or req...

Page 136: ......

Page 137: ... bus OUTGRANT is passed from one slot position n to the next n 1 now named INGRANT via the module placed in position n refer to the BINIDENT BOUTIDENT search The first module found with DMA request set is granted and is allowed to make a one word exchange Thus the INGRANT OUTGRANT daisy chain establishes a sequential priority scheme between the DMA controllers Refer to the illustration given in Fi...

Page 138: ......

Page 139: ...n explained As indicated this part is a handshake between the ECU and a requesting DMA controller The second part the transfer is a handshake between the granted DMA controller and memory BCU is passive during this part but monitors the time limit of release In the following text and illustrations the control signals relevant in the NORD lOO bus during a DMA transfer are described Due to some diff...

Page 140: ...memory system that the started reference is a read operation As soon as the DMA controller has removed its memory address this is done without feedback from memory the signal BDAPO is activated BDAPO Bus DAta Present means in a memory read cycle that memory may enable data to the BD lines This is also what the memory system is doing As the data is valid memory activates BDFIYo Bus Data ReadY The D...

Page 141: ...ycle is completed In order for the memory system to know when the data is valid the DMA controller combines the data with BDAPo ldata present BREO o I Ls _________________________ii BMEM o __ __ _ II lNGRANTO ll OUTGRANT o l I BOO 23 MEM ADDRESS DATATovEMORY Ii I BAPR o i i 1 ___f l l BlNPUT o i l H _ 4y Z BDAP 0 BDRYo l l l l l l l I l 80 LINES CONTAINS VALiD__ _ __ ____ DATA DATA TO MEMORY ACCEP...

Page 142: ......

Page 143: ...wledge Figure V 5 1 illustrates why the different signals are generated and how they are used Refer to Figure V 5 1 and note that the BCU is not involved in the memory refer ence The memory reference is handled by the granted DMA controller Further note that the only control signal in response from the memory system is BDRYO BDRY is the well known transfer completed and release bus signal which pr...

Page 144: ...m rlllil IIIIIII lllll III 0 p o mw oz 02 am Oh o3 r r _ moo 555 wmmmoc E m 586 7__ mmumz E sa E 51mm V 0s 5382 5 zofiomma 52 Saza E 5 555 z _ hz mukno E V F2552 _ n11 szoo A n t n 122 2552 2 Ezow1 25 5 1 xlgafiaafi inflame 535Q n 0 ti 2 2 H all 30 _ 25 mwszm 5W6 Enema 55 32m _ m5 3 03 a 20 IIY _ 2052 E fim fi o E 5 32 ommm m CEQE Eogmgéoxuowomwz 20 Ilv r I IIIIIIIIIIII m Ezefim 55 mm L 338 8 z_ mzm JJOI...

Page 145: ...osition card crate is selected Although 21 or often less than 12 modules are sufficient for most systems some configurantions require more space than even the 21 position card crate can offer This potential space problem is solved by the NORD 100 Bus EXtender BEX system The BEX system makes it possible to extend the NORD 100 bus structure by linking together from two to a theoretical maximum of 8 ...

Page 146: ......

Page 147: ...RATEH A CRATE INTERCONNECTION CABLES Figure VI 2 7 NORD 700 Bus Extender System Only one CPU can be connected to the Bus Extender System The crate where the CPU is located is referred to as the A crate The BEX module located in the A crate has to be BEX no 0 which defines it as the MASTER BEX From the MASTER BEX in crate A two cables are connected to BEX no I located in the next crate called crate...

Page 148: ... one of the search signals are received active by the MASTER BEX it means the actual search signal did not find stop condition in the A crate Thus the search is stopped in the A crate at the MASTER BEX s position and passed over to the next card crate NOTE 2 If the last l O device controller PlO or DMA or memory module is placed in the A crate position N the MASTER BEX should be placed in position...

Page 149: ...nctions are aimed against controlled routing of memory addresses when memory is partioned between several card crates In addition the response to different error situations may be set individually for each crate Some registers may be read for handling of error situations or configuration investigation Programmed access to the BEX modules has to be done by means of lOXT instructions device register...

Page 150: ... which corresponds to the memory area covered by the crate If a BEX is connected to a crate without memory the values set in the limit registers should be 0 to avoid unnecessary bus activity In addition to the Lower Limit and Upper Limit address registers each BEX contains a base register The value of the base register is used to give a positive offset to the address presented to a card crate The ...

Page 151: ...finds the address ok starts a memory cycle in its crate where memory is presented a crate address refer to Figure Vl 3 1 The crate address is calculated by the BEX as given below CRATE ADDR PRESENTED ADDR LL BASE For addresses below 1 M word Lower Limit LL is set equal to the base That is CRATE ADDR PRESENTED ADDR Only one answer from memory is ensured by the memory modules own lower upper limit a...

Page 152: ...ogram is the BEX number and the VITAL switch see the description Refer to Figure Vl 3 2 for physical placement of the switches the thumbwheel and the Light Emitting Diode LED indicator Refer also to the figure for associated abbreviations Lower Limit 0 w W m I m m m w k Y_JL__Y _ _I _ V__J MSS LSS WWW 9 fl LALLOW SWITCH VITAL SWITCH Upper Base 2 VITAL ON OFF INDICATOR 1 BEX NO THUMBWHEEL TH1 BASE S...

Page 153: ... Interrupt PFI in its lo cal crate If the switch is ON yellow LED not lit and a PFI occurs in a crate the connected BEX reports a PFI causing level 14 interrupt in the CPU if enabled That is as if the PFI occurred in the A crate If the VlTAL switch is OFF yellow LED lit the BEX sensing PFI reports this to be the CPU by an interrupt on level 13 It must then be decided by software how vital i e how ...

Page 154: ...played after a MASTER CLEAR or programmed DEVICE CLEAR The resolution of the switches is 64 K words per number turn on the least significant limit switch In Table Vl 3 1 a complete list is given for all the possible switch combinations The numbers given in the table correpsond to the displayed value by a given switch setting in either the Lower Limit Upper Limit or Base registers To get the corres...

Page 155: ...N MMN NMN PMN OMN NNN ON ON va MNN NNN FNN Om m N_ N ON ON EN EN NFN N OPN NON OON OON vON MON NON _ ON OON O NNF ONF ON VNF MNF NNP FNP ONF NO OOP OOF vO MOP NO_ OF OOF N NOF Om mmp VOF MOP NOF FOP OOP N3 O3 OE SV M3 N3 1 Q3 O NM OM OM QMP MM NM PMP OM NN ONF mN VNF MN NN PNF ON m N O m v M N _ _ _ O NO OOF OOF VOF M9 NO_ 5 OOF v NNO ONO ONO VNO MNO NNO _ NO ONO NOO OOO OOO OO MOO NOO FOO OOO M N...

Page 156: ... 13 2 Activate write data to selected register 3 Not Assigned 4 Clear Device 5 6 Mode see decoding below 7 8 Allow 9 External Interrupt Disable 10 15 Not Assigned Bit Description Bit 1 If this bit is set a level 13 interrupt will be generated if a parity error or local power fail interrupt is detected Bit 2 Activate Only used when writing memory limits into the selected limit register The selectio...

Page 157: ... BEX data register is moved to the register specified in the modus bit if the activate bit is set In a read operation the specified regsiters will be enabled onto the external bus during the next Read Data cycle Bit 8 Allow Should always be one Bit 9 External Interrupt Disable A possibility in software to disable interrupts from a specific crate STATUS REGISTER DEV NO 2 Bit No Function 0 Not Assig...

Page 158: ...s lower upper limit register or base register and A regsiter after a read of the same regi stars 15 8 7 0 NOT ASSIGNED LOWER LIMIT t READ WRITE LOWER LIMIT NOT ASSIGNED UPPER LIMIT READ WRITE UPPER LIMIT NOT ASSIGNED BASE WRITE BASE Lower upper limit and base values are in accordance with Table Vl 3 l Format of the A register after reading PES and PEA registers 15 0 LEAST MEMORY ADDRESS READ PEA 1...

Page 159: ... l l CRATE B _ _ _______ 1 r_____ ________ _ BEXNO O LI BEXNO 1 0 BASE DISPLAY I l I l 4 BASE DISPLAY l l l l l 4 UL DISPL AY 10 UL DlSPLAY I l l l 0 LL DISPLAY l 4 LL DISPLAY l l l l 0 I l l 4 BASE l l BASE 0 I I 0 l l 4 l l A K UL I l UL 0 l l l 0 l LL LL 0 i l l l 0 l l ___________u l MEMORY SETTINGS ____________ CRATE A MEMORY SETTINGS CRATE B 00 0 64k o4 64 128k 20 256 320k 10 128 192k 24 320...

Page 160: ......

Page 161: ...for ingoing ca bles and two for outgoing cables to the next crate The connectors used for ingo ing cables are marked AIN BIN The connectors used for outgoing cables are mar ked AOUT BOUT Refer to Figure Vl 5 1 for illustration CABLES TO _ NEXT CRATE 7 AOUT BOUT nag 4 M L1969 BEX 530m ADAPTER A MOUNTED IN PLUG PANEL s l 1 4 9 fl ____ r4 ___ __s 1 l l 6 C13 n lot lil 15 a s 2 é 5 9 13 l r CABLES FROM...

Page 162: ...al cable is equipped with a termination plug where each cable signal is terminated The termination plugs are physically connected to the internal cables approximately 10 cm from where they reach the BEX module Thus there is no need for termination in the last and open AOUT and BOUT ports Refer to Figure Vl 5 2 for an illustration of the internal wiring TERMINATION FLUGS lNTERNAL1 1 CABLE EXTERNAL ...

Page 163: ...GISTER ADDRESSES AND IDENT CODES In the following only the most frequently used Device Names are listed Two Device Names may use the same Device Register Address range In these cases only the most common Device Name is listed ND 06 016 01 ...

Page 164: ...10 12 7 60 Terminal 17 210 217 10 12 17 61 Terminal 18 220 227 10 12 52 62 Terminal 19 230 237 10 12 53 63 Terminal 20 240 247 10 12 54 64 Terminal 21 250 257 10 12 55 65 Terminal 2 260 267 10 12 56 66 Terminal 23 270 277 10 12 57 67 Terminal 24 300 307 10 12 1 1 120l Terminal 1 310 317 10 12 11 5 121 Terminal 2 TET 15 320 327 10 12 42 6 122 Terminal 3 TET 14 330 337 10 12 43 7 123 Terminal 4 TET ...

Page 165: ... Tape2 540 547 11 2 Drum1 550 557 11 6 Drum 2 560 577 12 13 1006 156 HDLC HASP1 600 607 11 22 4 Versatec1 610 617 11 11 Core to Core1 620 637 11 36 10 CDC I O Link 640 647 10 12 1040 124 Terminal 33 650 657 10 12 1041 125 TerminaI34 660 667 10 12 1042 126 Terminal 35 670 677 10 12 1043 127 TerminaI36 700 707 12 20 11 CATSY1 710 717 12 21 21 CATSY 2 720 727 11 23 E 8 S Pict Syst DMA 730 737 10 10 D...

Page 166: ...minal 28 1240 1247 10 12 74 74 Terminal 29 PHOTOS 1 1250 1257 10 12 75 75 Terminal 30 PHOTOS 2 1260 1267 10 12 76 76 Terminal 31 PHOTOS 3 1270 1277 10 12 77 77 Terminal 32 PHOTOS 4 1300 1307 10 12 60 50 Terminal 9 1310 1317 10 12 61 51 Terminal 10 1320 1327 10 12 62 52 Terminal 11 1330 1337 10 12 63 53 Terminal 12 1340 1347 10 12 64 54 Terminal 13 1350 1357 10 12 65 55 Terminal 14 1360 1367 10 12 ...

Page 167: ...y Disk 1 Unit 0 1 2 1570 1577 11 1003 1005 22 Floppy Disk 2 Unit 0 1 2 1600 1603 11 14 Versatec 2 1604 1607 HDLC Remote Load 1 1610 1613 HDLC Remote Load 2 1614 1617 HDLC Remote Load 3 1620 1623 HDLC Remote Load 4 1624 1627 HDLC Remote Load 5 1630 1633 HDLC Remote Load 6 1634 1637 HDLC Remote Load 7 1640 1657 12 13 150 HDLC NORD NET1 1660 1677 12 13 151 HDLC NORD NET2 1700 1717 12 13 152 HDLC NORD...

Page 168: ......

Page 169: ...emory management system and memory These registers are only accessed by privileged instructions and could not be accessed by an ordinary customer s program Internal registers can be accessed when the computer is in STOP or OPCOM mode For a detailed description refer to the manual NORD 100 Functional Description ND 06 016 01 ...

Page 170: ... programs while bits 8 15 are system dependent and only accessible by system TRA TRR Operator s register Implemented in firmware Display register Implemented in firmware Paging status register Paging control register Previous level The content of the register is IRR previous level 108 DP Internal interrupt code Internal interrupt enable Priority interrupt detect Priority interrupt enable Cache sta...

Page 171: ...cter is transferred to the A register The data available signal is reset if MOPC is not active IOX 301 No operation IOX 302 Read input status Bit 0 1 data available will give interrupt when it occurs Bit 3 1 data is available ready for transfer ls never given if MOPC is active 4 1 inclusive or of error bits 5 7 Bit 5 1 framing error Bit 6 1 parity error Bit7 1 overrun Bits 1 2 and 8 15 are always ...

Page 172: ...ignifies 2 1 5 for 5 bits stop bits Bit 14 1 a parity bit is added to the number of bits mentioned above Bit 14 0 no extra bit is added to the bits mentioned above IOX 304 Returns 0 in the A register and has no other effect IOX 305 Write data according to input control word setting lOX 306 Read output status Bit 0 1 ready for transfer will give interrupt when it occurs Bit 3 1 ready for transfer B...

Page 173: ...0 4 or 8 Asynchronous Current Loop Programming Specifications TERMINAL ADDRESS CODES The IOX dev no relevant for different terminals is found in Appendix A The device number dev no is selected by a thumbwheel Device number and corresponding thumbwheel settings are given in Appendix D 2 2 INPUT CHANNEL INTERRUPTLEVEL 12 Read Data Register IOX dev no 0 The number of data bits read into the A registe...

Page 174: ...v no 6 See paragraph describing Status registers Write Control Register IOX dev no 7 See paramter describing control registers DATA RATE SELECTION IOX dev no 1 DENT CODE The ident code for the input channel and the output channel will be the same with the input channel responding to level 12 and the output channel responding to level 10 The selection of different ident codes are given in the parag...

Page 175: ...rror 6 Parity error 7 Overrun 8 9 10 11 12 Not used 13 14 15 Note Additional explanation to status bits Bit 5 Framing error means that the stop bit is missing Bit6 Parity error means that a parity error has occurred while working in parity generating checking mode Bit7 Overrun means that at least one character is overwritten while input is active ND 06 016 01 ...

Page 176: ...ted for one of the four interfaces all four will be set in test mode The content of these bits gives the following character lengths both for the input channel and the output channel Bit 12 Bit 11 O 0 8 bits 0 1 7 bits 1 0 6 bits 1 1 5 bits If bit 14 is a 1 a parity bit is added to the number given in this table This bit 0 will select 1 5 stop bits for 5 bits character and 2 stop bits otherwise Th...

Page 177: ...5 Not used Bit 3 This bit indicates that the output data buffer is ready to receive a new character Con trol Register Bit 0 Enable interrupt on device ready for transfer 1 15 Not used Note The device is activated when a character is loaded into the output character register There is no need for separate activation ND 06 016 01 ...

Page 178: ...v RFT Test 4 ERR OR 5 Framing 6 Parity 7 Overrun 8 9 10 11 Character length 12 Character length 13 Stop bits 14 Parity generation check 15 Output Bit Status Control 0 RFT enable Enable RFT 1 2 3 Device RFT 4 ERR OR 5 Framing 6 Parity 7 Overrun 8 9 10 11 12 13 14 15 ND 06 016 01 ...

Page 179: ...dy to be read into the A register For output it means that it is possible to place at least one more character in the output buffer Secondly interrupt on ready for transfer must be control register bit 0 which also is status register bit 0 The AND function of ready for transfer and ready for transfer interrupt enabled is gated to put it connected to interrupt level 12 terminal 35 and output is con...

Page 180: ...a bits read into the A register is specified by bits 11 and 12 in the input channel control register The received character is right justified from bit 0 and upwards Read Status Register lOX dev no 2 Write Control Register IOX dev no 3 OUTPUT CHANNEL INTERRUPTLEVEL 70 Write Data Register IOX dev no 5 The number of bits specified by bits 11 and 12 in the input channel control register is written to...

Page 181: ...error 6 Parity error 7 Overrun 8 9 Not used 10 11 Carrier missing 13 14 Not used 15 Note Additional explanation to status bits Bit 5 Framing error means taht the stop bit is missing Bit 6 Parity error means that a parity error has occurred while working in parity generation checking mode Bit 7 Overrun means that at least one character is overwritten while input is active Bit 11 Carrier missing giv...

Page 182: ...ill be st in test mode If this bit is activated the DATA TERMINAL READY signal will drop after approximately 20 seconds if no characters are received The content of these bits give the following character lengths both for the input channel and the output channel Bit 12 Bit 11 O O 8 bits 0 1 7 bits 1 0 6 bits 1 1 5 bits If bit 14 is a 1 a parity bit is added to the number given in this table This b...

Page 183: ... 15 Not used N KO Bit 3 This bit indicates that the output data buffer is ready to receive a new character Bit 11 As forinput channel Contro Register Bit 0 Enable interrupt on device rc ady for transfer 115 Not used Note The device is activated when a character is loaded into the output character register There is not need for separate activation ND 06 016 01 ...

Page 184: ...OR Start time out 5 Framing 6 Parity 7 Overrun 8 9 10 11 Carrier missing Character length 12 Character length 13 Stop bits 14 Parity generation check 15 Output Bit Status Control 0 RFT enable Enable RFT 1 2 3 Dev RFT 4 ERR OR 5 Framing 6 Parity 7 Overrun 8 9 10 11 Carrier missing 12 13 14 15 ND 06 016 01 ...

Page 185: ...nnection If signal detector and DSR are high the first input character has to be received within 20 seconds If not DIR will go low for approximately 6 seconds and reamin oscillating with 20 seconds high and 6 seconds low until an input character is received Must be high when NORD transmitted data High will give high on RTS Low will give low on RTS and a steady high on DTR Must be high when NORD re...

Page 186: ... Read Status Word lOX DEV NO 2 Bit 0 Interrupt enabled on ready Bit 1 Interrupt enabled on error Bit 2 Not used Bit 3 Ready for transfer Bit 4 Error bit 5 or 6 set Bit 5 Line printer not ready Bit 6 Out of paper Bit 7 Compressed pitch Bit 8 LP9 is on to indicate to the controller that data on the lines is format information and is interpreted as control code Bit 9 Inhibit illegal character in buff...

Page 187: ... the interface except the following control codes 118 HT gives space in CDC controller 128 LF 148 FF 158 CR 208 338 VFU channels give LP9 and disable LP5 208 VFU channel 1 FF 213 338 VFU channel 12 Read Data Word IOX DEV NO 0 It is possible to read back the data written in the buffer when running in test mode bit 3 set in control word ND 06 016 01 ...

Page 188: ...ss has to be loaded by two consecutive IOX 501 The most significant 8 bits are loaded by the first lOX 501 The least significant 16 bits are loaded with the next IOX 501 lOX 501 Read Sector Counter IOX 502 Load Block Address IOX 503 Read Status Register IOX 504 Load Control Word lOX 505 Read Block Address IOX 506 Load Word Counter Register IOX 507 The minimum number of words to be transferred is o...

Page 189: ...r Bit 1 Enable interrupt on errors Bit 2 Activate device Bit 3 Test mode Bit 4 Device clear Bit 5 Not assigned Bit 6 Not assigned Bit 7 Marginal recovery Bit 8 Not assigned Bits 9 10 Unit select Bits 11 12 Device operation Bit 13 Not assigned Bit 14 Not assigned Bit 15 Write format Unit Select Code Bit 10 9 Bit 0 0 Unit 0 Bit 0 1 Unit 1 Bit 1 0 Unit 2 Bit 1 1 Unit 3 Device Operation Code Bit 12 11...

Page 190: ...5 11 Bit 5 Write protect violate Bit 6 Time out Bit 7 Missing clock Disk fault Seek error Bit 8 Address mismatch Bit 9 Parity error Bit 10 Compare error Bit 11 DMA error Bit 12 Transfer complete Bit 13 Transfer on Bit 14 On cylinder Bit 15 Bit 15 loaded by previous control word Interrupt The disk interrupt level is 11 and the ident number for the first disk system is 1 ND 06 016 01 ...

Page 191: ...C 1 APPENDIX C SWITCH SETTINGS FOR THE DIFFERENT NORD IOO MODULES SWITCHES ON THE CPU MODULEI3002 r ALD CONSOLE n u 1 P I ND 06 016 01 ...

Page 192: ...oad from 1600 Binary load from 1600 9 Start in address 20 8 Start in address 20 7 100000 Stop Stop Nothing 6 101560 Binary load from 1560 Binary load from 1560 Binary load from 1560 5 120500 Mass load from 500 Mass load from 500 Mass load from 500 4 121540 Mass load from 1540 Mass load from 1540 Mass load from 1540 3 100400 Binary load from 400 Binary load from 400 Binary load from 400 2 101600 Bi...

Page 193: ... B Lawest lOX address J H1915 0X 6732 Second lowest lOX nd hi 5 was lOX 1 Floppy disk system 2 2 terminal group 3 2 initial band rate for terminals C 2 1 7 Floppy Disk System 0 floppy system no 1 10X1560 1567 IDENT 21 1 2 floppy system no 2 10X 1570 1577 IDENT 22 2 15 are unused will answer on 10X 0 7 ND 06 016 01 ...

Page 194: ...baud 10 200 baud 11 134 5 baud 12 75 baud 13 50 baud 14 unused 15 unused IOX 300 337 IOX 340 377 IOX 1300 1337 IOX1340 1377 IOX 640 677 IOX 1100 1137 IOX1140 1177 lOX1400 1437 IOX 1500 1537 IOX1640 1677 IOX 1700 1737 IOX1740 1777 IOX 200 237 IOX 240 277 IOX1200 1237 IOX 1240 1277 Selector switches for current loop R8232 C Switch set to 0 selects current loop Switch set to 1 selects R8232 C Switch ...

Page 195: ...scription is correct for the 2 position switch If a hexadecimal switch is used 0 currentloop F R8232 C If component houses are used 16 a o Selects current loop 1 6 Q 6 O O Selects RS 232 C 1 I a O ND 06 016 01 ...

Page 196: ... memory address Upper limit is automatically displayed according to actual memory size The limit address increments are 16K units such that Octal Address 2 40 000 x limit Lower limit Size Upper limit 0 0 16K 0 1 O 0 32K 0 2 0 0 64K 0 4 0 3 32K 0 5 0 3 64K 0 7 3 4 64K 4 0 ND 06 016 01 Address range 0 16K 0 32K 0 64K 48 80K 48 112K 448 512K ...

Page 197: ...l be Slot Lower limit Size Upper limit Address Range 12 88 64K 04 0 64K 11 88 64K 10 64 128K 10 88 64K 14 9 88 64K 20 8 88 64K 24 7 88 64K 30 6 88 64K 34 384 448K 5 88 64K 40 448 512K etc SWITCHES ON THE 70MB DISK MODULE 3004 THUMBWHEEL SWITCH lc ll 3 ll A l Switch pos 0 device no 500 507 ident no 1 disk system 1 l Switch pos 1 device no 510 517 ident no 5 disk system 2 Switch pos 215 not used IOX...

Page 198: ...Switch pos 2 15 not used lOX address bit 15 active will inhibit this card SWITCH SETTING ON NORD 100 BUS ADAPTER 3008 DlP SWITCH P05 80 4 3 2 ON calaiiai Switch 1 off 0 device no s 3777 0 S ident no s 377 Switch 1 on 2000 S device no 3777 400 ident no S 777 Switch 2 2 off normal Switch 2 on block all interfaces on this bus Switches 3 and 4 not used lOX address bit 15 active will inhibit this card ...

Page 199: ...H 2 PCS 80 11311A i Switch 1 off 0 Sdevice no 1777 0 ident no S 377 Switch 1 on 2000 device no 3777 400 ident no 777 Switch 2 off normal Switch 2 on block all interfaces on this bus Switches 3 and 4 not used IOX address bit 15 active will block this card ND 06 016 01 ...

Page 200: ......

Page 201: ...APPENDIX D NORD IOO PLUG PANEL FOR EXTERNAL DEVICE CONNECTION A FLOPPY DISK 4 TERMINALS 1 3 CONSOLE TERMINAL CABLE ND 06 016 01 ...

Page 202: ......

Page 203: ...the rows are marked at the right short edge The row letters start with A at the plug edge and end with H at the edge towards you The column numbers are marked at the long edge towards you starting with 1 at the right corner and ending up with 28 in the left corner The row letters and column numbers are printed on the module Sometimes however the letters and numbers are not printed This is because ...

Page 204: ...n E2 The arrangement drawing for a NOR D 100 module identifies the type of integrated circuit occupying each coordinate position on the module The type of integrated circuit is written on the circuit at each location The arrangement drawings have the same coordinate system as the modules They are drawn from the component side with the plug edge to the left Make sure you are looking at the arrangem...

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Page 207: ... CW TRACK 6 SOCKET ORRECTIONS ACCORDING TO EC 0 NO DAVE SIGN DESIGNED BY PJJ EE 30x 40x E 1 m M 1 E m i I I MxMKAHG CORRECTIONS WITHOUT EC 0 VERSION NO DESCRIPTION 0 AWN BY 8W ND 06 016 01 02 12 80 m E m P f of 0 SIZE L e Y 5 I 193193512 1 0333 It Q s I 24 _ 120 25 amv gts lVQfIV cm wasaH DATE SIGN ...

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Page 209: ...LE 10w CARD PRINI NORSK DATA A S 8 TERMINAL INTERFACE 322513 K H f 1 1010 so so 7022 slug 4 90 mil2 1 22 2222 2 1 2 2 l I Ig3 2222 731 g 1IM IIIIIIIIII I 8132 WJIiéééIIIILIIIII 3 SE CD fl MFW EEEEEEEEE 35432522222222 33143 m 9 dHQ L 3 EECO 3 7 217057GF v I T D 745 259 V 9 dDOUO HBQNDN 33M 30 53 8w 50y MIQJZ C7 E 60y 32440 5 1 2K R50 V d Db Q BNUN 33 430 I I 2222 20 2 MI W éS 2 _ffiofijfm 27 E II 1 28...

Page 210: ...E 8 E 3 NO TA T ON OF SIGNALS TO AND FROM NORD 700 MODULES COMPONENT SIDE w 4k 4r r NORD 1OO O BACKPLANE BUS o Examp_ g DB 150 RDAT 71 CH 6 Bc18 ND 06 016 01 ...

Page 211: ...DONONONDWOWOWOWGDDI DOWDQODOWONONOWGWDN 64 wire flatcable A pair shielded round cable Remarks HO kha B cormector on 3010 B B A cormector on 3013 26 ll 79 ND06 016 01 Drawing No 4 TERMINAL INTERFACES FOR N lOO 3 9322 DEVICE PLUG C J B F EMALE MODEM 35 PUT IN N Pin 1 in the device plug is connected to cable shLeld In the computer end of the external cable the shield is connected to an earth strap wi...

Page 212: ...e Plud 25 P POLARITY ELTRUPLL G Fartinfil Cover PIN No 75wnj1 1 nluq mom a C a C a C a C a C a C a C a C a C a C a C a C a C a C a C a 64 wire flatcable Pin 1 in the device plug is connec to cable shield 4 pair round cable with screen In the commuter and of the external cable the shield is connected to an earth strap fasten x Strap in external cable Remarks Replacement for Date B connector on 3010 ...

Page 213: ...llowing page All logic signals are in the active low polarity i e Logical 0 2 4 to 5 0 volts Logical 1 0 to 0 5 volts The normal TTL noise margins are assumed but it is recommended to use receivers with hysteresis on sensitive inputs especially on signals that are at 1 while the data bus switches Maximum load 2 0 8 mA for each slot ND 06 016 01 ...

Page 214: ... BINT I3 I C 17 PANREQ c BLANK I I l BINT 15 I C 18 BINPUI CI CM BPERR M CX i BDAP CI MI 19 BDRY MI CI BINACK C I BIOXE c I 20 BAPR CI MI BMCL CI CMI BMEM C MI 21 INCONTR E E 1 BERROR E E OUTCONTR E a 22 INIDENT CI BCRQ E E OUTIDENT CI I 23 INGRANT CI I BMINH P CM OUTGRANT CI I 24 GND P CMI GND P CMI GND P CMI 25 15V P CMI 15v P CMI 15v P CMI 26 An Return P I An Return P I An Return P I 27 15v P C...

Page 215: ...ave been accepted given by answering device Wired OR line BDO 23 Multiplexed data and address bus Bit 0 is least significant BERROR Bus Error signals that an error was detected during a bus cycle e g fatal memory error Wired OR line BINACK Bus Input Acknowledge signals that an interface requesting an input operation may enable data Generated by controlling unit BINPUT Bus Input signalled by a unit...

Page 216: ... Clear button is pushed Wired OR line BMEM Bus Memory Cycle signals that a bus cycle accesses memory Generated by controlling unit BMlNH Bus Memory Inhibit used to inhibit memory accesses during power down and power up sequence in systems which have battery backup for memory only Generated by controlling unit BPERR Bus Parity error Fatal or correctable error from memory according to the ECC regist...

Page 217: ...r removed from controlling unit INGRANT originates as OUTGRANT from controlling unit lNlDENT Response to BlNT10 13 together with address bits 0 5 which specify BINT number An interface which issued BINT on the specified level prior to the last leading edge of BAPR shall respond by enabling its lDENT CODE onto the BD bus Otherwise lNlDENT is passed on to OUTlDENT which is connected to lNlDENT of th...

Page 218: ...SPARE Not assigned STOP Forces the CPU to enter STOP mode after completion of the current instruction Wired OR line only in CPU crate 5V Main logic supply voltage 5V Standby Logic supply voltage for memory retention during power fail 15V Supply voltage for analogue interface circuits For customer use 15V Supply voltage for analogue interface circuits For customer use 12V Standby Supply voltage for...

Page 219: ...s The lines in the 24 bits multiplexed address and data bus is named BOO 23 BDO denotes the least significant bit while 8023 denotes the most significant bit The Contra Lines Each control line has their own unique name and function see Appoendix F 2 Generally a signal name is an abbreviation of its function preceeded by a B for Bus example BREQ _ Bus REQuest Signal Po ar ty As stated in Section F ...

Page 220: ...Timing Diagrams The representation of control signals in a timing diagram is as shown below LEADING EDGE TRAlLlNG EDGE BREOO 17 V BREQ1 __ _l L TY 1L Y 1L Y J NOT NOT ACTIVE ACTIVE ACTIVE The BDO 23 lines are represented as shown below p IL L J V Y Y NO BD LINES NO INFORMATION lNFORMATlON CONTAINS DATA ND 06 016 01 ...

Page 221: ...APPENDIX G SCHEMATICS ND 06 016 01 ...

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Page 242: ......

Page 243: ...You will receive a membership card and an answer to your comments HHHH HELP YOURSELF BY HELPING US NHHHfifl Manual name ND lOO Input Output System Manual number ND 06 016 01 What problems do you have use extra pages if needed Do you have suggestions for improving this manual Your name Date Company Position Address What are you using this manual for NOTE Send to This form is primarily for Norsk Data ...

Page 244: ...Answer from Norsk Data Answered by Date Norsk Data A S Documentation Department PO Box 25 Bogerud 0621 Oslo6 Norway ...

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