DETAILED DESCRIPTION
2-15
Block diagram:
Figure 2-3 NMP110A block diagram.
Block description:
FREQUENCY DIVIDER
divides the system clock (3.6864MHz) into 30Hz, 90Hz, 150Hz, 1020Hz, morse code tick
length and morse code word length clock signals.
IDENT SEQUENCER
generates the programmed ident envelope for the ILS signal and external DME equipment.
CONTROL SECTION
includes the RMS interface, address decoding, configuration control and automatic refresh of
the DACs and the other registers. The refresh cycle is performed after a completed RMS
access cycle.
2.3
OS1221
B
RF Oscillator
General Description:
The OS1221B module generates the RF signals used for the generation of the carrier signals
in the transmitters (ch. 2.5).
Configuration
Storage
Counter
Ident Sequencer
Refresh Address
Sequencer
RMS interface
DME_IDNT_IN, DME_ACTIVE
Address
Decoder
MUX
EXT_SERVICE
*_CS,DAC_A
IOCSB
CLK
TST30
CLR90
CLR150
COU90
COU150
IDNT_DIG
DME_IDNT_OUT
IDNT_ON
IOS*
IOD*
Control
Control Section
Frequency Divider
ADDR*
COAX_POS, LF_ADDR
HBK563-1
