Chapter 4
Connecting the Signals
4-32
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CONVERT* Signal
Any PFI pin can externally input the CONVERT* signal, which is
available as an output on the PFI2/CONVERT* pin.
Refer to Figures 4-15 and 4-16 for the relationship of CONVERT* to the
sequence.
As an input, CONVERT* is configured in edge-detection mode. You can
select any PFI pin as the source for CONVERT* and configure the polarity
selection for either rising or falling edge. The selected edge of CONVERT*
initiates an A/D conversion.
As an output, CONVERT* reflects the actual convert pulse that connects to
the ADC, even if the conversions are externally generated by another PFI.
The output is an active low pulse with a pulse width of 50 to 100 ns. This
output is set to high-impedance at startup.
Figures 4-23 and 4-24 show the input and output timing requirements
for CONVERT*.
Figure 4-23.
CONVERT* Input Signal Timing
Figure 4-24.
CONVERT* Output Signal Timing
Rising-Edge
Polarity
Falling-Edge
Polarity
t
w
= 10 ns minimum
t
w
t
w
= 50 to 150 ns
t
w
