NEX 6620A User's Guide
Rev. B0 0301
BIOS Setup
4-14
DRAM Clock
The chipset supports synchronous and asynchronous mode between host clock and DRAM clock
frequency.
Host CLK
The DRAM clock will be equal to the Host Clock.
HCLK-33M
The DRAM clock will be equal to the Host Clock
minus 33MHz. For example, if the Host Clock is
133MHz, the DRAM clock will be 100MHz.
HCLK+33M
The DRAM clock will be equal to Host Clock plus
33MHz. For example, if the Host Clock is 100MHz,
the DRAM clock will be 133MHz.
By
SPD
BIOS automatically determine the DRAM clock
frequency by SPD IC on the DRAM card.
DRAM Timing
Selects whether the SPD IC on the DRAM card or Manual controls DRAM timing.
Selecting
Manual
allows you to control SDRAM Cycle Length and Bank Interleave by yourself.
It is strongly suggested to select
By SPD
to avoid causing any system error.
The Choice: Manual, By SPD.
SDRAM Cycle Length
Controls the time delay (in clock cycles) before SDRAM starts a read command after receiving it.
The Choice: 3, 2.5, 2.
Bank Interleave
Enables or disables bank interleave feature.
The Choice: Disabled, 2 Bank, 4 Bank.
►►
AGP & P2P Bridge Control
Press <Enter> to enter the sub-menu, and you will see a sub-menu.
AGP Aperture Size
Select the size of Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI
memory address range dedicated for graphics memory address space. Host cycles that hit the
aperture range are forwarded to the AGP without any translation.
