LIS-SDI Rev.
2
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4. A more detailed description
4.1 Data path
SDI-IN is equalized and reclocked, then transferred bit serially to the FPGA. The FPGA
descrambles and deserializes the input to 10-bit parallel, detects whether it is 625/50Hz or
525/60Hz, and writes the data to the line-buffer.
Data is fetched from the line-buffer, EDH is checked, the data is transferred to a chip that
serializes and scrambles the signal, and drives the resulting 270 Mb/s SDI-signal onto the
output connectors.
4.2 EEPROM
The LIS-SDI card actually has two EEPROM's. A small EEPROM is included in the
microcontroller, while a larger external EEPROM holds the configuration memory of the
FPGA and the input video chip.
Internal EEPROM
State variables are written to EEPROM in the microcontroller each time a configuration
change is made. Basically, the card remember it's setting between power-downs.
External EEPROM
The configuration memory of the FPGA and the input video chip is upgradeable. This is,
however, a task for qualified maintenance personnel.
4.3 Two modes of operation
The LIS-SDI can operate in two modes, with or without linesync (switch 3 or lsync on/off
command). When the linesync mode is off the card is used as a deglitcher. Then the output
phase is not adjustable.
It is recommended that the Black&Burst is connected also when the card is just used as a
deglitcher. The Black&Burst will insure that the output frequency is correct even if the input
signal is lost. When the linesync mode is off, the SDI output is delayed by half a line with
respect to the first SDI input detected. Any SDI used as input to the deglitcher must not be off
phase by more than half a line with respect to any other input presented to the deglitcher.
When the linesync mode is turned on the LIS-SDI is used as a line synchroniser and a
deglitcher. The output is synchronized to the Black&Burst. The output phase is adjustable
over a full frame with respect to the Black&Burst. The internal video buffer is only one line
long. Therfore the phase of the output SDI must be from 41 samples to 1 line and 41 samples
after the input SDI. The internal processing delay is 41 samples. It is important to know the
phase of the input SDI signals.
An example:
If the SDI inputs have a phase with respect to Black&Burst that is 0 lines and 0 samples, then
the user could for instance set the output phase to 0 lines and 700 samples.
