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network-electronics.com

HD-SDI to SD-SDI

Down-converter

Rev. 2

Flashlink User Manual

DWC-HD

Summary of Contents for DWC-HD-DMUX

Page 1: ...network electronics com HD SDI to SD SDI Down converter Rev 2 Flashlink User Manual DWC HD...

Page 2: ...cs com www network electronics com Support Phone 47 90 60 99 99 Revision history Current revision of this document is the uppermost in the table below Rev Repl Date Sign Change description 2 1 2008 07...

Page 3: ...5 3 9 EDH processing block 15 3 10 Video output selection 15 3 11 Video DAC 17 3 12 Audio overview 17 3 13 Audio de embedder 17 3 14 Audio delay 17 3 15 Audio cross point matrix 17 3 16 Audio fallback...

Page 4: ...uirements for Network Electronics equipment 33 Product Warranty 34 Appendix A Materials declaration and recycling information 34 A 1 Materials declaration 34 A 2 Recycling information 35 EC Declaratio...

Page 5: ...swapped in an audio matrix before they are re embedded in the SD SDI data output stream For SD SDI inputs it is possible to turn embedding completely off and leave the SDI stream unaltered A selection...

Page 6: ...D down converter With high sensitivity 9 125 m single mode optical input 2XSDI out SD HD analog out internal audio handling analog stereo out AES or RS 422 data out and frame synchronizer functionalit...

Page 7: ...15dB 5MHz 1 5GHz SD limit Jitter tolerance 10Hz 1kHz 1 UI 10kHz 5MHz 0 2 UI HD limit 10Hz 100kHz 1 UI 100kHz 10MHz 0 2 UI Electrical Sync input Connector 75 Ohm BNC Format Black Burst Tri level Input...

Page 8: ...ic range 100dB A Crosstalk 60dB 20Hz 20kHz THD N 70dB Frequency response 20Hz 20kHz 0 5dB Output level 24dBu 1dB Common mode DC 0 48V immunity Level adjustment range 0 24dBu with 1db step Two tone int...

Page 9: ...P168 tri level SMPTE 170M ITU R BT 470 definition and sync AES AES3 1996 Optical SMPTE 297M SMPTE 292M EDH Compliant to SMPTE RP165 Video Payload SMPTE 352M 2002 Identification Other Power consumption...

Page 10: ...dio DAC and the AES out respectively 3 1 2 When down converting HD video The video is routed to a Scaling block and the resulting SD video is passed to a Frame synchronizer block If video is missing a...

Page 11: ...uld be switched to the next priority The rules are lol loss of lock los loss of signal EDH Errors are found in the video frame Hold time determines how long a signal has to be missing unlockable conta...

Page 12: ...94p or 1080 24p the output will be 486 29 97i The following assumes that the aspect ratio of the incoming HD is 16 9 and that the pictures are such that objects are shown geometrically correct on a 1...

Page 13: ...r the pattern selected in Video generator will be output Defaults are optical input as first priority then electrical and finally fallback to Black video with a Hold time of 3 seconds Note that input...

Page 14: ...a frame roll If a sync input appears Given that a stable SDI input exists If a sync signal appears the delay mode will change to Frame Sync mode see Chapter 3 6 1 Hence the internal clock will be lock...

Page 15: ...video updates the EDH flags according to SMPTE RP165 and inserts the EDH package into the ancillary data of the video If disabled The EDH processing block only reads process and report the EDH packag...

Page 16: ...When input is HD the Auto mode will insert WSS data according to the selected aspect ratio in the scaler block When the input is SD the Auto mode will signal 4 3 or 16 9 based on the aspect ratio bit...

Page 17: ...his will obviously cause audio errors 3 15 Audio cross point matrix The audio cross point matrix is a 10x10 cross point with inputs and outputs as shown in Figure 4 The 8 de embedded channels a 1 kHz...

Page 18: ...channel is phase inverted MM Left Right 2 Both channels replaced with the mean of left and right MS MS AB Conversion from AB stereo to MS stereo 3 19 Audio embedder The audio embedder can be enabled...

Page 19: ...3 4 Aspect ratio DIP 3 4 Off Off 16 9 DIP 3 4 Off On 4 3 DIP 3 4 On Off 16 9 LB DIP 3 4 On On Previous setting preserved Previous setting preserved With DIPs in this position before the module is boot...

Page 20: ...taining to DIPs and the rotary switch 16 OVR Off GYDA mode This DIP is only read at power up On Manual mode OVR is short term for GYDA override 4 2 FACTORY reset function A factory reset is a 3 step p...

Page 21: ...les the signal when in AES mode Note that to enable Data link output on the AES connector it is also necessary to set DIP 8 to the Off position when the board is in Manual mode DIP 16 On or when the b...

Page 22: ...eo delay represents the actual delay between input and output video The audio de embedders 1 4 show the state of the audio control package for their associated audio group de embedded from the input s...

Page 23: ...SDI output 1 inverted HD SD SDI output 2 O2 BNC ____ O2 BNC HD SD SDI output 2 inverted Analog video Y G CVBS Y G CVBS BNC Analog video Pb B Y PB B Y BNC Analog video Pr R C PR R C BNC WECO Audio con...

Page 24: ...dded in incoming video 4 audio groups embedded in incoming video Module not programmed or DIPs 14 15 both set to the On position Audio input status 6 2 RS422 commands 6 2 1 FLP4 0 required commands Co...

Page 25: ...update filename filename dwchddmux 0 105 ffw name extensio n The name part must match the card s hardware and include a revision number and the extension must be either ffw for FPGA firmware or mfw fo...

Page 26: ...ts if the change over is latching or not used when change over is automatic Latch on means that if we ve lost our main source and moved on to a lower priority level we ll not search to see if the high...

Page 27: ...o other settings but the priority list pri k l cho 5 pri 0 2 0 from audio matrix 1 sine 2 black 3 kill Note Only generators pri 1 2 or 3 are allowed to be set as first and only priority Audio common f...

Page 28: ...ea emb 2 dis acp on off emb 1 acp on emb 3 acp off use24 on off emb 1 use24 on acp on off This is valid only for SD and enables the audio control package emb 2 use24 off del off on del12 del34 emb 0 d...

Page 29: ...lines lines samples sps dly 2 1lines 30sps phase lines lines samples sps If lines 0 the resulting phase will vary with incoming video standard see dly 0 above Internal video generator vgen 0 cbar vge...

Page 30: ...iBel referred to full scale output Units are optional but if included must be written as cBFS case sensitive Audio processing aprc 0 9 lr aprc 0 lr lr rl aprc 3 ll rl one block for each output from ch...

Page 31: ...single word or byte from a SPI registers to check register status Addressing is 16b and most significant nibble determines which chip These are the address ranges 0x0000 0x0fff audio DAC 0x1000 0x1ff...

Page 32: ...fication under the following environmental conditions Operating room temperature range 0 C to 45 C Operating relative humidity range 90 non condensing 2 The equipment will operate without damage under...

Page 33: ...d conditions for the product s covered by this manual follow the General Sales Conditions by Network Electronics AS These conditions are available on the company web site of Network Electronics AS www...

Page 34: ...oxic or hazardous substance contained in at least one of the homogeneous materials used for this part is above the limit requirement in SJ T11363 2006 This is indicated by the product marking A 2 Recy...

Page 35: ...C HARMONISED STANDARDS applied in order to verify compliance with Directive s EN 55103 1 1996 EN 55103 2 1996 TEST REPORTS ISSUED BY Notified Competent Body Report no Nemko E08463 00 TECHNICAL CONSTRU...

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