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UME-0027-03 XCM6040SAT2
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4.4 Digital Processing flow in FPGA
The figure below shows the
digital processing flow in the FPGA.
Figure 4-4-1 FPGA Processing Block Diagram
4.5 Startup
After turning on, the camera runs a startup procedure before it starts getting
images and outputting data.
It takes about four seconds.
The startup procedure is as follows.
(1) The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory. (User
settings if any or factory default settings)
(3) Sets up the camera with the setting values from the flash memory.
After this sequence, the camera is ready to get images and output data.
Video(10bit)
From
Sensor
-
x
White reference
multipl
Test Pattern
select
Black reference
substract
FPGA Processing block diagram
x
Video(8 or 10bit)
To Channel Link
Driver
Digital Gain
-
Digital Offset
8 or 10bit
select
Output Block
select
In Test Pattern mode, Black / White reference and Digital Gain /Offset will be skipped.
