NED
XCM8060SA_8040SA_6040SA
UME-0034-03
38
4.4 Digital Processing flow in FPGA
The figure below shows the
digital processing flow in the FPGA.
Video(10bit)
From Sensor
-
x
White reference
multipl
Test Pattern
select
Black reference
substract
FPGA Processing block diagram
x
Video(8 or 10bit)
To Channel Link
Driver
Digital Gain
-
Digital Offset
8 or 10bit
select
Output Block
select
In Test Pattern mode, Black / White reference and Digital Gain /Offset will be skipped.
Figure 4-4-1 FPGA Processing Block Diagram
4.5 Startup
After turning on, the camera runs a startup procedure before it starts getting
images and outputting data. It takes about four seconds.
The startup procedure is as follows.
(1) The camera initializes the hardware.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
(3) Sets up the camera with the setting values from the flash memory.
After this sequence, the camera is ready to get images and output data.
4.6 Saving and Loading Camera Settings
The camera setting data is saved in the internal memory (flash memory) and is
loaded from the memory when turning on the power supply or loading (sending the
“rfd” command).
The number of times the flash memory can be rewritten will vary depending
on actual operational conditions. After turning on the power supply, the camera
always checks the memory status. If the data is not within the
designated range
due to a malfunction or other type of trouble, the memory will be automatically
rewritten with the factory settings.
If disconnecting camera power while rewriting the memory, all data saved in
the memory will be deleted.
