40
NED
XCM2085DLMT2
UME-0059-02
4.2.21 Setting Output Data Rate
Set the output data rate.
Format 2 CMD
□
VAL1 CR
CMD clkcl
VAL1 85,40 (85:85MHz / 40:40MHz)
<Example>
clkcl
□
40 CR (at 40MHz)
>OK
>clkcl 40
4.3 Digital Processing flow in FPGA
The digital processing flow in FPGA is shown below.
Figure 4-3-1 FPGA Processing Block Diagram
Note: When Test Pattern is selected, Black/White reference, Digital Gain & Offset are
omitted.
Video(8,10bit)
To Channel Link
Driver
Video (8bit)
