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NEC V850E/CA2 JUPITER, Preliminary User'S Manual

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585

Chapter 17

RESET

Preliminary User’s Manual U15839EE1V0UM00

17.4  Reset by RESET Pin

If a low-level signal is input to the RESET pin, a system reset is performed and the hardware is initial-
ized. When the RESET pin level changes from low to high, the Reset State is released and the program
execution is started. All register will be initialized. The RESET pin incorporates a noise eliminator, which
uses analogue delay to prevent malfunction due to noise.

(1)

Reset signal acknowledgment

Figure 17-1:

Reset signal acknowledgment

Note: The internal system reset signal keeps its active level for at least four system clock cycles after

a RESET pin is released.

RESET

Internal system
reset signal

Elimination as noise

Reset acknowledgment

Reset release

Analog 
delay

Analog 
delay

Analog 
delay

Note

Summary of Contents for V850E/CA2 JUPITER

Page 1: ...reliminary User s Manual V850E CA2TM JUPITER 32 16 bit Romless Microcontroller Hardware PD703128 PD703129 Document No U15839EE1V0UM00 Date Published August 2003 NEC Corporation 2003 Printed in Germany...

Page 2: ...ote No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence...

Page 3: ...ereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient...

Page 4: ...588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espa a Madrid Spain Tel 091 504 27 87 Fax 091 504...

Page 5: ...ed as follows Weight in data notation Left is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address H...

Page 6: ...6 Preliminary User s Manual U15839EE1V0UM00...

Page 7: ...3 4 3 Wrap around of CPU address space 67 3 5 Memory Map 68 3 5 1 Area 70 3 5 2 Recommended use of address space 75 3 5 3 Peripheral I O Registers 76 3 5 4 Programmable peripheral I O registers 83 3...

Page 8: ...67 Chapter 7 DMA Functions DMA Controller 169 7 1 Features 169 7 2 Control Registers 170 7 2 1 DMA source address registers H0 to H3 DSAH0 to DSAH3 170 7 2 2 DMA destination address registers H0 to H3...

Page 9: ...terrupt Edge Detection Control Registers 223 8 5 Software Exception 227 8 5 1 Operation 227 8 5 2 Restore 228 8 5 3 Exception status flag EP 229 8 6 Exception Trap 230 8 6 1 Illegal opcode definition...

Page 10: ...3 4 Control registers 313 10 3 5 Output delay operation 321 10 3 6 Explanation of basic operation 322 10 3 7 Operation in Free run mode 324 10 3 8 Match and clear mode 335 10 3 9 Edge noise eliminati...

Page 11: ...14 3 5 CAN Module Registers 485 14 4 Operating Considerations 509 14 4 1 Rules to be observed for correct baud rate settings 509 14 4 2 Example for baudrate setting of CAN module 510 14 4 3 Ensuring...

Page 12: ...577 16 3 12Port CT 579 16 3 13Port CM 581 Chapter 17 RESET 583 17 1 Reset Overview 583 17 2 Features 583 17 3 Pin Functions 583 17 4 Reset by RESET Pin 585 17 5 Reset by Watchdog Timer 587 17 6 Reset...

Page 13: ...in Word 117 Figure 4 6 Little Endian Addresses within Word 117 Figure 4 7 Example of Wait Insertion 133 Figure 5 1 Example of Connection to SRAM 138 Figure 5 2 SRAM External ROM External I O Access Ti...

Page 14: ...nterrupt Is Being Processed 1 2 213 Figure 8 9 Example of Processing Interrupt Requests Simultaneously Generated 215 Figure 8 10 Interrupt Control Register xxIC 216 Figure 8 11 Interrupt Mask Register...

Page 15: ...Operation 1 2 302 Figure 10 24 Block Diagram of Timer Gn 308 Figure 10 25 Timer Gn Counter 0 Value Registers TMGn0 310 Figure 10 26 Timer Gn Counter 1 Value Registers TMGn1 310 Figure 10 27 Timer Gn c...

Page 16: ...eption Completion Interrupt Timing 380 Figure 13 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 381 Figure 13 13 When Reception Error Interrupt Is Included in INTSRn I...

Page 17: ...ure 14 20 Internal CAN Test Bus Structure 466 Figure 14 21 CAN Interrupt Pending Registers CCINTPL CCINTPH 467 Figure 14 22 CAN Global Interrupt Pending Register CGINTP 1 2 468 Figure 14 23 CAN 1 to 4...

Page 18: ...onfiguration 546 Figure 16 2 Type A Block Diagram 551 Figure 16 3 Type B Block Diagram 552 Figure 16 4 Type C Block Diagram 553 Figure 16 5 Type D Block Diagram 554 Figure 16 6 Type E Block Diagram 55...

Page 19: ...rol Register PMCCT 580 Figure 16 38 Port CM PCM 581 Figure 16 39 Port CM Mode Register PMCM 582 Figure 16 40 Port CM Mode Control Register PMCCM 582 Figure 17 1 Reset signal acknowledgment 585 Figure...

Page 20: ...20 Preliminary User s Manual U15839EE1V0UM00...

Page 21: ...n WATCH Mode 261 Table 9 10 Operation after SUB WATCH mode release by interrupt request 262 Table 9 11 Operating States in STOP Mode 265 Table 10 1 Timer C Configuration List 274 Table 10 2 TOC0 Outpu...

Page 22: ...e Handling upon Reception into a Transmit Message Buffer 451 Table 14 16 CAN Message Processing by TRQ and RDY Bits 476 Table 14 17 Address Offsets of the CAN 1 to 4 Mask Registers 486 Table 15 1 A D...

Page 23: ...0E CPU supports the RISC instruction set and through the use of basic instructions that can each be executed in 1 clock period and an optimized pipeline achieves marked improvements in instruction exe...

Page 24: ...sociative 4K Bytes Boot Loader Internal Boot Loader for downloading Flash Self Programming routines into RAM Support of virgin programming for external flash memories Clock Generator Internal Spread S...

Page 25: ...t counter 2 channel 16 bit multi purpose timer counter 1 channel 16 bit OS timer 2 channel Watch timer 1 channel Watchdog timer 1 channel Interrupts and exceptions Non maskable interrupts 2 source Mas...

Page 26: ...of sophisticated periph eral functions and CAN network support is required 1 4 Ordering Information Part number Package Internal ROM bytes Internal RAM bytes Full CAN RAM bytes Channels PD703128 A 14...

Page 27: ...ANI9 P82 ANI10 P83 ANI11 MODE0 P97 AVREF AVSS AVDD VDD30 VSS30 P94 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53...

Page 28: ...or Power Supply SI00 SI01 SI02 Serial Input CVSS Clock Generator Ground SO00 SO01 SO02 Serial Output GND30 to GND36 Ground for 3 V Power Supply TIG00 to TIG05 TIG10 to TIG05 TIC00 TIC01 Timer Input GN...

Page 29: ...TMC 16 bit Timer TMG1 TIG10 to TIC15 TOG11 to TOG14 TIC00 TIC01 TOC00 16 bit Timer TMD1 16 bit Timer TMD0 FCAN2 FCAN1 FCRXD1 FCTXD1 FCRXD2 FCTXD2 UART51 UART50 RXD50 TXD50 RXD51 TXD51 CSI00 SI00 SO00...

Page 30: ...8 to 128 bytes b DMA controller DMAC Instead of the CPU this controller controls data transfer between memory and I O There is one address mode 2 cycle transfer and there are three bus modes single t...

Page 31: ...11 Ports As shown below the following ports have general port functions and control pin functions Port Port Function Control Function Port 1 8 bit input output Serial interface input output Port 2 8 b...

Page 32: ...32 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 33: ...XD1 P11 FCTXD1 P12 FCRXD2 P13 FCTXD2 P14 FCRXD3Note P15 FCTXD3Note P16 RXD1 P17 TXD1 P20 I O Port 2 8 bit input output port SI0 P21 SO0 P22 SCK0 P23 SI1 P24 SO1 P25 SCK1 P26 RXD0 P27 TXD0 P30 I O Port...

Page 34: ...NTP0 P62 INTP1 P63 INTP2 P64 INTP3 P65 SI2 P66 SO2 P67 SCK2 P70 I Port 7 8 bit input port ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 P80 I Port 8 4 bit input port ANI8 P81 ANI...

Page 35: ...PAH5 A21 PAH6 A22 PAH7 A23 PCS0 I O Port CS 3 bit input output port CS0 PCS3 CS3 PCS4 CS4 PCT0 I O Port CT 3 bit input output port LWR PCT1 UWR PCT4 RD PCM0 I O Port CM 1 bit input output port WAIT Ta...

Page 36: ...e input for A D converter NMI input non maskable interrupt input P60 ANI0 ANI7 input analog input to A D converter P77 to P70 ANI8 ANI11 input analog input to A D converter P80 to P83 SI00 input seria...

Page 37: ...0 capture input 3 P33 TOG03 TIG04 input Timer G 0 capture input 4 P34 TOG04 TIG05 input Timer G 0 capture input 5 P35 TOG05 TOG01 output Timer G 0 compare output 1 P31 TIG01 TOG02 output Timer G 0 co...

Page 38: ...trobe signal for lower byte bit 0 bit 7 PCT0 UWR output Write strobe signal for upper byte bit 0 bit 7 PCT1 RD output Read strobe signal for external bus PCT4 WAIT input Control signal input for exter...

Page 39: ...te INTP15 to INTP10 N A operate operate operate operate operate operate INTP21 to INTP20 N A operate operate operate operate operate operate INTP5 to INTP0 N A operate operate operate operate operate...

Page 40: ...control register PMC1 a Port mode P10 to P17 can be set to input or output in 1 bit units using the port 1 mode register PM1 b Control mode P10 to P17 can be set to port or control mode in 1 bit units...

Page 41: ...mode control register PMC2 a Port mode P20 to P27 can be set to input or output in 1 bit units using the port 2 mode register PM2 b Control mode P20 to P27 can be set to port or control mode in 1 bit...

Page 42: ...or control mode can be selected for each bit and specified by the port 3 mode control register PMC3 a Port mode P30 to P35 can be set to input or output in 1 bit units using the port 3 mode register...

Page 43: ...or control mode can be selected for each bit and specified by the port 4 mode control register PMC4 a Port mode P40 to P45 can be set to input or output in 1 bit units using the port 4 mode register...

Page 44: ...0 to P56 can be set to input or output in 1 bit units using the port 5 mode register PM5 b Control mode P50 to P56 can be set to port or control mode in 1 bit units using PMC5 c TO0 Timer output Outpu...

Page 45: ...control register PMC6 a Port mode P60 to P67 can be set to input or output in 1 bit units using the port 6 mode register PM6 b Control mode P60 to P67 can be set to port or control mode in 1 bit unit...

Page 46: ...re not switchable c ANI0 to ANI11 Analog Input 0 to 11 These are the analog input pins for the A D converter Connect a capacitor between AVDD and AVSS to prevent noise related operation faults Also do...

Page 47: ...he address bus on an external access 10 PCS0 PCS3 PCS4 Port CS Input output Port CS is a 3 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in con...

Page 48: ...This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM external ROM or an external peripheral I O area e RD Read strobe Output This is a strobe signal that shows th...

Page 49: ...release a standby mode HALT IDLE Watch Sub Watch software STOP 16 RESOUT Reset Output RESOUT output is a 3 3 V reset output signal It is the internal system reset output RESOUT is active low in case...

Page 50: ...round pins for the 3 3 V power supply 26 AVDD Analog power supply This is the analog positive power supply pin for the A D converter 27 AVSS Analog ground This is the ground pin for the A D converter...

Page 51: ...or VSS5 via a resistor For output leave open P11 FCTXD1 P12 FCRXD2 P13 FCTXD2 P14 FCRXD3 P15 FCTXD3 P16 RXD51 P17 TXD51 P20 SI00 5 K P21 SO00 P22 SCK00 P23 SI01 P24 SO01 P25 SCK01 P26 RXD50 P27 TXD50...

Page 52: ...nput individually connect to VDD5 or VSS5 via a resistor For output leave open P81 ANI9 P82 ANI10 P83 ANI11 P90 5 K For input individually connect to VDD5 or VSS5 via a resistor For output leave open...

Page 53: ...N11 9 C MODE0 2 MODE1 2 connect to VSS5X via a resistor MODE2 2 VDD3X RESET 2 RESOUT 3 connect to VDD3x via a resistor X2 16 Please refer to the datasheet XT1 16 Please refer to the data sheet XT2 16...

Page 54: ...pe 4 Data Output disable V P ch N ch IN OUT DD Type 5 data output disable input enable VDD P ch IN OUT N ch Type 5 K Data Output disable V P ch N ch IN OUT DD VSS Input enable Type 9 C P ch N ch Input...

Page 55: ...ne control 3 1 Features Minimum instruction cycle 31 25 ns internal 32 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general registers Internal 32 bit...

Page 56: ...3 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Assembler Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter...

Page 57: ...en used 2 Program counter This register holds the instruction address during program execution The lower 26 bits of this register are valid and bits 31 to 26 are fixed to 0 If a carry occurs from bit...

Page 58: ...CTPC use the even value bit 0 0 Remark O Access allowed Access prohibited Table 3 2 System Register Numbers No System Register Name Operand Specification LDSR Instruction STSR Instruction 0 Status sav...

Page 59: ...U15839EE1V0UM00 Figure 3 3 Interrupt Source Register ECR Bit Position Bit Name Function 31 to 16 FECC Exception code of non maskable interrupt NMI 15 to 0 EICC Exception code of exception maskable int...

Page 60: ...eration result of a saturated operation processing instruction is sat urated due to overflow Due to the cumulative flag if the operation result is saturated by the saturation operation instruction thi...

Page 61: ...sult Status of Operation Result Flag Status Saturation Processed Operation Result SAT OV S Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Positive maxi...

Page 62: ...oot Loader offering the possibility to download programming algorithms and the new ROM code itself To be able to use this feature there s no need to have already a dedicated boot software being progra...

Page 63: ...o program erase the contents of the external memory device it is required to enable a Flash Pro gramming Mode The following operation modes are generally available for the V850E CA2 Jupiter device a P...

Page 64: ...ace Data and instructions in the internal boot ROM cannot be accessed or fetched 3 FLASH Programming Mode 0 In FLASH Programming Mode 0 external flash memory programming is enabled by starting from th...

Page 65: ...p to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3...

Page 66: ...the image of the virtual addressing space Physical address x000 0000H can be seen as CPU address 0000 0000H and in addition can be seen as address 0400 0000H address 0800 0000H address F800 0000H or...

Page 67: ...us like this Figure 3 7 Wrap around of Program Space Caution No instruction can be fetched from the 4 KB area of 03FF F000H to 03FF FFFFH because this area is defined as peripheral I O area Therefore...

Page 68: ...reserves areas as shown in Figure 3 9 1 For PD703128 Figure 3 9 Memory Map PD703128 A x3FF FFFFH Internal peripheral I O area Internal RAM area External memory area Single chip mode 64 Mbytes 4 Kbytes...

Page 69: ...For PD703129 Figure 3 10 Memory Map PD703129 A PD703129 A1 x3FF FFFFH Internal peripheral I O area Internal RAM area External memory area Single chip mode 64 Mbytes 4 Kbytes x3FF F000H x3FF EFFFH x000...

Page 70: ...d an interrupt exception table which is located in the external ROM area When an interrupt exception request is accepted execution jumps to the handler address and the program written at that memory i...

Page 71: ...sion end 0000 0260H MAC Interrupt CGINTP 1 2 0000 0270H CAN1 Receive Interrupt 0000 0280H CAN1 Transmit Interrupt 0000 0290H CAN1 Error Interrupt 0000 02A0H CAN2 Receive Interrupt 0000 02B0H CAN2 Tran...

Page 72: ...0H DMA Channel 1 transfer completed 0000 03E0H DMA Channel 2 transfer completed 0000 03F0H DMA Channel 3 transfer completed 0000 0400H DMA Overflow 0000 0410H P30 0000 0420H P35 0000 0430H P40 0000 04...

Page 73: ...FF AFFFH are reserved for the internal RAM area In the PD703129 the 16 KB of addresses 3FF 8000H to 3FF BFFFH are provided as internal physical RAM Figure 3 11 Internal RAM Area of PD703129 Figure 3 1...

Page 74: ...ss of the word area ignoring the lower 2 bits of the address 2 For registers in which byte access is possible if half word access is executed the higher 8 bits become undefined during the read operati...

Page 75: ...64 MB space starting from address 0000 0000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be performed through the wrap around...

Page 76: ...BHC R W 0000H FFFF F06E CPU VPB Strobe Wait Control register VSWC R W 77H FFFF F070 Instruction Cache Control Register ICC R W 0003H FFFF F072 Instruction Cache Index Register ICI R W FFFFH FFFF F074...

Page 77: ...control register 1 TMD0IC R W 47H FFFF F114 Interrupt control register 2 TMD1IC R W 47H FFFF F116 Interrupt control register 3 WTIIC R W 47H FFFF F118 Interrupt control register 4 P0IC R W 47H FFFF F...

Page 78: ...errupt control register 42 FC4ERIC R W 47H FFFF F166 Interrupt control register 43 CSI0IC R W 47H FFFF F168 Interrupt control register 44 CSI1IC R W 47H FFFF F16A Interrupt control register 45 CSI2IC...

Page 79: ...t 6 mode PM6 R W FFH FFFF F42E Port 9 mode PM9 R W FFH FFFF F440 Port 1 mode control PMC1 R W 00H FFFF F442 Port 2 mode control PMC2 R W 00H FFFF F444 Port 3 mode control PMC3 R W 00H FFFF F446 Port 4...

Page 80: ...0L R W 00H FFFF F643 TMGCM0H R W 00H FFFF F644 Output control register OCTLG0 R W 0000H OCTLG0L R W 00H FFFF F645 OCTLG0H R W 00H FFFF F646 State register TMGST0 R 00H FFFF F648 Timer Count Register 0...

Page 81: ...W 00H FFFF F842 DMA trigger source select register 1 DTFR1 R W 00H FFFF F844 DMA trigger source select register 2 DTFR2 R W 00H FFFF F846 DMA trigger source select register 3 DTFR3 R W 00H FFFF F880...

Page 82: ...FF FD44 Transmission data buffer register SOTB1 SOTBL1 R W 0000H 00H FFFF FD48 First transmission data buffer register SOTBF1 SOTBFL1 R W 0000H 00H FFFF FD4A Shift register SIO1 SIOL1 R O 0000H 00H FF...

Page 83: ...le peripheral I O area The base address of the programmable peripheral I O area is specified by the initialization of the peripheral area selection control register BPC Figure 3 15 Programmable Periph...

Page 84: ...he programmable peripheral area is located at 180 0000H Therefore the FCAN macro is mapped to the memory location 180 0000H to 180 11FFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BPC...

Page 85: ...message ID register H00 M_IDH00 R W x Undefined xxxxn014H CAN message configuration register 00 M_CONF00 R W x Undefined xxxxn015H CAN message status register 00 M_STAT00 R x Undefined xxxxn016H CAN...

Page 86: ...N message event pointer 030 M_EVT030 R W x Undefined xxxxn061H CAN message event pointer 031 M_EVT031 R W x Undefined xxxxn062H CAN message event pointer 032 M_EVT032 R W x Undefined xxxxn063H CAN mes...

Page 87: ...message event pointer 052 M_EVT052 R W x Undefined xxxxn0A3H CAN message event pointer 053 M_EVT053 R W x Undefined xxxxn0A4H CAN message data length register 05 M_DLC05 R W x Undefined xxxxn0A5H CAN...

Page 88: ...ssage data length register 07 M_DLC07 R W x Undefined xxxxn0E5H CAN message control register 07 M_CTRL07 R W x Undefined xxxxn0E6H CAN message time stamp register 07 M_TIME07 R W x Undefined xxxxn0E8H...

Page 89: ...essage time stamp register 09 M_TIME09 R W x Undefined xxxxn128H CAN message data register 090 M_DATA090 R W x Undefined xxxxn129H CAN message data register 091 M_DATA091 R W x Undefined xxxxn12AH CAN...

Page 90: ...message data register 111 M_DATA111 R W x Undefined xxxxn16AH CAN message data register 112 M_DATA112 R W x Undefined xxxxn16BH CAN message data register 113 M_DATA113 R W x Undefined xxxxn16CH CAN me...

Page 91: ...message data register 133 M_DATA133 R W x Undefined xxxxn1ACH CAN message data register 134 M_DATA134 R W x Undefined xxxxn1ADH CAN message data register 135 M_DATA135 R W x Undefined xxxxn1AEH CAN m...

Page 92: ...message data register 155 M_DATA155 R W x Undefined xxxxn1EEH CAN message data register 156 M_DATA156 R W x Undefined xxxxn1EFH CAN message data register 157 M_DATA157 R W x Undefined xxxxn1F0H CAN m...

Page 93: ...AN message data register 177 M_DATA177 R W x Undefined xxxxn230H CAN message ID register L17 M_IDL17 R W x Undefined xxxxn232H CAN message ID register H17 M_IDH17 R W x Undefined xxxxn234H CAN message...

Page 94: ...essage ID register H19 M_IDH19 R W x Undefined xxxxn274H CAN message configuration register 19 M_CONF19 R W x Undefined xxxxn275H CAN message status register 19 M_STAT19 R x Undefined xxxxn276H CAN st...

Page 95: ...N message status register 21 M_STAT21 R x Undefined xxxxn2B6H CAN status set cancel register 21 SC_STAT21 W x 0000H xxxxn2C0H CAN message event pointer 220 M_EVT220 R W x Undefined xxxxn2C1H CAN messa...

Page 96: ...message event pointer 240 M_EVT240 R W x Undefined xxxxn301H CAN message event pointer 241 M_EVT241 R W x Undefined xxxxn302H CAN message event pointer 242 M_EVT242 R W x Undefined xxxxn303H CAN mess...

Page 97: ...message event pointer 262 M_EVT262 R W x Undefined xxxxn343H CAN message event pointer 263 M_EVT263 R W x Undefined xxxxn344H CAN message data length register 26 M_DLC26 R W x Undefined xxxxn345H CAN...

Page 98: ...ssage data length register 28 M_DLC28 R W x Undefined xxxxn385H CAN message control register 28 M_CTRL28 R W x Undefined xxxxn386H CAN message time stamp register 28 M_TIME28 R W x Undefined xxxxn388H...

Page 99: ...ssage time stamp register 30 M_TIME30 R W x Undefined xxxxn3C8H CAN message data register 300 M_DATA300 R W x Undefined xxxxn3C9H CAN message data register 301 M_DATA301 R W x Undefined xxxxn3CAH CAN...

Page 100: ...ind start register CGMSS W x 0000H xxxxn101AH CAN message find result register CGMSR R x 0000H xxxxn101CH CAN test bus register CTBR R W x x 0000H xxxxn101DH CAN Macro Version Register CGREV R x x Rev...

Page 101: ...register C2BA R x x 00FFH xxxxn109CH CAN2 bit rate prescaler register C2BRP R W x x 0000H xxxxn109DH CAN2 bus diagnostic information register C2DINF R x x 0000H xxxxn109EH CAN2 synchronization control...

Page 102: ...r H2 Note 2 C4MASKH2 R W x x Undefined xxxxn11CCH CAN4 address mask register L3 Note 2 C4MASKL3 R W x x Undefined xxxxn11CEH CAN4 address mask register H3 Note 2 C4MASKH3 R W x x Undefined xxxxn11D0H...

Page 103: ...nd therefore the PRCMD register has to be written first The following 5 NOPs are necessary for waken from the STOP mode Example 1 MOV 0x02 r10 2 ST B r10 PRCMD r0 3 ST B r10 PSC r0 4 NOP dummy instruc...

Page 104: ...gister is read Only the first write access to a specific on chip register hereafter referred to as a specific register after data has been written to the PRCMD register is valid In this way the value...

Page 105: ...referred to as a specific register after data has been written to the PHCMD register is valid In this way the value of the specific register can be rewritten only in a specified sequence and an illeg...

Page 106: ...r is not written to causing a protection error Writing 0 to the PRERR flag after the value is checked clears the error Operation conditions of PRERR flag Set condition 1 If the most recent store instr...

Page 107: ...0 Address R W Reset Value VSWC 0 SUWL2 SUWL1 SUWL0 0 VSWL2 VSWL1 VSWL0 FFFFF06EH R W 77H 0 1 1 1 0 1 1 1 Bit Name Description SUWL2 SUWL1 SUWL0 Setup wait for internal peripheral bus length SUWL2 SUW...

Page 108: ...inary User s Manual U15839EE1V0UM00 Table 3 8 The Values of VSWC Register depending on System Clock System Clock Setup Wait Strobe Wait VSWC 4 0 MHz fCPU 16 6 MHz 0 0 00H 16 6 MHz fCPU 25 0 MHz 0 1 01...

Page 109: ...for each memory block External wait function through WAIT pin Idle state insertion function External device connection can be enabled via bus control port alternate function pins 4 2 Bus Control Pins...

Page 110: ...000H 39FF FFFH 3800 000H 37FF FFFH 3400 000H 33FF FFFH 3000 000H 2FFF FFFH 2800 000H 27FF FFFH 1000 000H 0FFF FFFH 0C00 000H 0BFF FFFH 0400 000H 03FF FFFH 0200 000H 01FF FFFH 0000 000H Block 1 2 Mbyte...

Page 111: ...rder is controlled as follows CSC0 Peripheral I O area CS0 CS2 CS1 CS3 Note CSC1 Peripheral I O area CS7 CS5 CS6 CS4 Note Notes 1 Not all the chip area select signals are externally available on outpu...

Page 112: ...access CS23 CS2 active during block 3 access CS30 CS3 active during block 0 1 2 or 3 access CS31 CS3 active during block 4 or 5 access CS32 CS3 active during block 6 access CS33 CS3 active during bloc...

Page 113: ...is allocated to the last 4 KB of the programmable peripheral I O register area Figure 4 3 Programmable Peripheral I O Register Outline Cautions 1 The programmable peripheral area must not be located...

Page 114: ...rammable peripheral area is mapped to x1800000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BPC PA15 0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FFFFF064H 0000H Bit P...

Page 115: ...nd BCT1 registers is finished However it is possible to access external memory areas whose initialization has been finished 2 The bits marked as 0 are reserved They have to leave to 0 15 14 13 12 11 1...

Page 116: ...BSC register is finished However it is possible to access external memory areas whose initialization has been finished 2 When the data bus width is specified as 8 bits only the LWR signal becomes acti...

Page 117: ...Little Endian format n 0 to 7 3 In the following areas the data processing method is fixed to Little Endian method Any setting of Big Endian method for these areas according to the BEC register is in...

Page 118: ...an format CS area and CS areas set as the following areas ROM area RAM area Peripheral I O area Programmable peripheral I O area 2 The bits marked as 0 are reserved They have to leave to 0 Note n 0 to...

Page 119: ...starting from the lower order side 1 Byte access 8 bits a When the data bus width is 16 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 b When the data bus width is 8 bits...

Page 120: ...dress 2n 2 Access to odd address 2n 1 d When the data bus width is 8 bits Big Endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7...

Page 121: ...ress 2n 1 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 7 0 7 0 Halfword data 15 8 External data...

Page 122: ...Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 15 8 2n 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2...

Page 123: ...15 8 External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Ad...

Page 124: ...ss 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0...

Page 125: ...24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word dat...

Page 126: ...a External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus...

Page 127: ...rnal data bus 4n 3 Addres 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 1 Address 15 8 4n 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8...

Page 128: ...ss 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0...

Page 129: ...31 24 7 0 7 0 Word data External data bus 4n 1 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word da...

Page 130: ...a External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus...

Page 131: ...e settings of registers DWC0 and DWC1 are invalid wait control is performed by each memory controller Page ROM on page access 3 Write to the DWC0 and DWC1 registers after reset and then do not change...

Page 132: ...ten in 16 bit units Remark During address setup wait the external wait function is disabled by the WAIT pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ASC AC71 AC70 AC61 AC60 AC51 AC5...

Page 133: ...etup hold time at sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 8 3 Relationship between programmable wait and external wait A wait cycle is inserted a...

Page 134: ...tically programmed for all memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Cautions 1 The internal iCache area the internal RAM area and the internal p...

Page 135: ...ty has the DMA cycle instruction fetch and operand data access in this order An instruction fetch may be inserted between read access and write access during read modify write access Also an instructi...

Page 136: ...Data space The V850E CA2 Jupiter is provided with an address misalign function Through this function regardless of the data format word data halfword data or byte data data can be placed in all addres...

Page 137: ...kes a minimum of 2 states Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers Data wait can be controlled with input pin WAIT Up to 3 idle states c...

Page 138: ...to SRAM a When data bus width is 16 bits b When data bus width is 8 bits Remark CSn CS0 CS3 and CS4 2 Mbit SRAM 256 Kwords x 16 bits V850E CA2 D0 to D15 CSn LWR UWR LBE UBE RD WE A1 to A17 A1 to A17...

Page 139: ...ure 5 2 SRAM External ROM External I O Access Timing 1 6 a During read Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1...

Page 140: ...I O Access Timing 2 6 b During read address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS...

Page 141: ...ROM External I O Access Timing 3 6 c During write Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Address Data WAIT...

Page 142: ...I O Access Timing 4 6 d During write address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and C...

Page 143: ...OM External I O Access Timing 5 6 e When read write operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Addres...

Page 144: ...OM External I O Access Timing 6 6 f When write read operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Addres...

Page 145: ...5 2 1 Features Direct connection to 8 bit 16 bit page ROM supported In case of 16 bit bus width 4 8 16 32 64 word page access supported In case of 8 bit bus width 8 16 32 64 128 word page access suppo...

Page 146: ...f Page ROM Connections a In case of 16 bit data bus width b In case of 8 bit data bus width Remark CSn CS0 CS3 and CS4 A0 to A19 O1 to O16 CE OE 16 Mbit page ROM 1 Mword x 16 bits A1 to A20 D0 to D15...

Page 147: ...of 16 Mbit 1 M 16 bits page ROM 4 word page access b In case of 16 Mbit 1 M 16 bits page ROM 8 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal ad...

Page 148: ...M 16 bits page ROM 16 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal address latch immediately preceding address V850E CA2 address output Page R...

Page 149: ...mory areas whose initialization has been finished 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value PRC 0 PRW2 PRW1 PRW0 0 0 0 0 0 0 0 0 MA6 MA5 MA4 MA3 FFFFF49AH 7000H Bit Position Bit Name...

Page 150: ...rd word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and...

Page 151: ...bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 TW O...

Page 152: ...f word word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3...

Page 153: ...e access with 8 bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3...

Page 154: ...154 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 155: ...hm replaces the cache line that has not been used since the longest time The probability of a instruction cache hit is mostly higher compared to the direct mapped type Using the tag clear function the...

Page 156: ...s performance the V850E CA2 Jupiter device provides a 4 KByte 2 way associative instruction cache memory The instruction cache is organ ized as 4 words x 128 entries x 2 ways Figure 6 1 Instruction C...

Page 157: ...has two ways each consisting of a block of 128 entries of 4 words per line for a total capacity of 4 KB Figure 6 2 Configuration of 4 KB 2 Way Set Associative Instruction Cache INDEX TAG 3 0 1 2 10 1...

Page 158: ...ng bit 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ICC 0 0 0 LOCK0 0 0 0 0 0 0 0 FILL0 0 0 TCLR1 TCLR0 FFFFF070H 03H Bit Position Bit Name Function 12 LOCK0 This bit shows the cache...

Page 159: ...e Initial Register ICI The ICI register controls the iCache operation by the MODE bit The ICI register can be accessed by 16 bit access Figure 6 5 Instruction Cache Initial Register ICI Caution All bi...

Page 160: ...g the cache configuration register BHC 2 Operation on Instruction Cache Hit 1 On a fetch access from memory the CPU outputs the instruction fetch request and the concerned address to the instruction c...

Page 161: ...truction cache to the BCU 3 The BCU then outputs the address to external memory via the VSB and refills the instruction cache with one line 4 words at the address to be read 4 The instruction cache th...

Page 162: ...uction Cache 16 bit Data Bus Remarks 1 The numbers within pointed brackets indicate the refill sequence 2 Adrs n Data of address in n 0H to FH 128 entries Higher address Lower address Data part 4 word...

Page 163: ...Note a Set the TCLR0 bit b Read the TCLR0 bit to confirm that this bit is cleared c Perform a and b above again d Set the TCLR1 bit e Read the TCLR1 bit to confirm that this bit is cleared f Perform d...

Page 164: ...2 Second TAG clear 13 Id h ICC r0 r1 14 cmp r0 r1 15 bnz LOP2 Remark The clock count required for a tag clear operation is 256 clocks To actually clear tags the required clock count is doubled because...

Page 165: ...and confirm that bit is cleared 0 Remarks 1 A lock is released by clearing bit LOCK0 of the ICC register 2 While the iCache autofill operation is ongoing neither interrupt nor NMI will be served by C...

Page 166: ...t 1 Wait until the contents of the ICC register becomes 0000H TAG initialization is completed 2 Clear all bits of the ICI register using the following instruction st h r0 0xfffff072 r0 3 Set the ICC a...

Page 167: ...ICCNote Instruction cache data configuration register ICD Note Excluding bit 4 3 Initial program settings Always execute the following instruction before setting the cache configuration register BHC w...

Page 168: ...d if the memory boundary is continuously accessed by instruction other than a branch instruction An example is shown below Suppose that the cache area settings are as shown in figure iCache Area Setti...

Page 169: ...ransfer units 8 16 and 32 bits Maximum transfer count 65 536 216 Two types of transfer two cycle transfer Four transfer modes Single transfer mode Single step transfer mode Line transfer mode Four bus...

Page 170: ...l I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 7 1 DMA Source Address Registers DSAH0 to DSAH3 DSAH0 to DSAH3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH0...

Page 171: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL1 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address I...

Page 172: ...egister image 3FFF000H to 3FFFFFFH must not be specified Figure 7 3 DMA Destination Address Registers 0H to 3H DDA0H to DDA3H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH0 IR 0 0 0...

Page 173: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL1 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Init...

Page 174: ...ied 2 For a setting of the DBCn register in which the transfer count cannot be divided by 4 the sections that can be line transferred are line transferred first then the remaining indivisible sections...

Page 175: ...DAD1 DAD0 TM1 TM0 0 0 FFFFF0D2H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DADC2 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D4H 0000H 15 14 13 12 11 10 9 8 7 6 5...

Page 176: ...ration Remark n 0 to 3 Bit Position Bit Name Function 5 4 DAD1 DAD0 Sets the count direction of the destination address for DMA channel n n 0 to 3 DAD1 DAD0 Count Direction 0 0 Increment 0 1 Decrement...

Page 177: ...through DMA channel n has ended or not It is read only and is set to 1 when DMA transfer ends and cleared 0 when it is read 0 DMA transfer had not ended 1 DMA transfer had ended 3 MLEn When this bit...

Page 178: ...g the ENn bit of the corresponding channel to 1 This register can be read written in 8 bit or 1 bit units Figure 7 9 DMA Restart Register DRST Remark n 0 to 3 7 6 5 4 3 2 1 0 Address Initial value DDI...

Page 179: ...are is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR0 register set tings 2 An interrupt re...

Page 180: ...are is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR1 register set tings 2 An interrupt re...

Page 181: ...is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR2 register set tings 2 An interrupt reque...

Page 182: ...e is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR3 register set tings 2 An interrupt requ...

Page 183: ...written with the value that was set immediately before Therefore during DMA transfer transfer is automatically started when a new DMA transfer setting is made for these registers and the MLEn bit of t...

Page 184: ...n the last T2R state read data is sampled After entering the last T2R state the bus invariably enters the T1W state 6 T2RI state State in which the bus is ready for DMA transfer to on chip peripheral...

Page 185: ...nsfers If the next transfer is executed in block transfer mode the DMAC moves to the T1FH state after the T2FH state In other modes if a wait has occurred the DMAC transitions to the T1FHI state If no...

Page 186: ...M00 7 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 7 15 DMAC Bus Cycle State Tr...

Page 187: ...ted lower priority DMA transfer request Figure 7 16 Single Transfer Example 1 on page 187 shows a DMAC transfer in single transfer mode In this example the DMA channel 3 is used for a single transfer...

Page 188: ...ed within one clock after the end of a sin gle transfer DMA channels 0 2 and 3 are used for this single transfer example When three or more DMA transfer request signals are activated at the same time...

Page 189: ...a DMA transfer example in single step transfer mode Figure 7 20 Single Step Transfer Example 1 Figure 7 21 Single Step Transfer Example 2 on page 189 shows a DMA transfer example in single step trans...

Page 190: ...released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figure 7 22 Line Transfer Example 1 on page 190 shows a DMA transfer example in line transfer mode F...

Page 191: ...for the line transfer example Figure 7 24 Line Transfer Example 3 DMA channel 0 in Figure 7 25 Line Transfer Example 4 on page 191 is used for a single transfer and channel 3 is used for the line tran...

Page 192: ...ends and the DMAC releases the bus and another DMA transfer can be acknowledged Figure 7 26 Block Transfer Example on page 192 shows a block transfer mode example It is a block transfer mode example i...

Page 193: ...one clock idle period is always inserted between a read cycle and a write cycle 7 7 Transfer Object 7 7 1 Transfer type and transfer object Table 7 1 Relationship Between Transfer Type and Transfer Ob...

Page 194: ...while the bus is released in the TI state the higher priority DMA transfer request is acknowledged 7 9 DMA Transfer Start Factors There are two types of DMA transfer start factors as shown below 1 Req...

Page 195: ...bit is set the next DMA transfer request is acknowledged and DMA transfer begins Figure 7 27 Example of Forcible Interruption of DMA Transfer Caution To forcibly interrupt DMA transfer and stop the ne...

Page 196: ...register Figure 7 28 DMA Transfer Forcible Termination Example 1 Remarks 1 The next condition can be set even during DMA transfer because the DSAn DDAn and DBCn registers are buffered registers Howev...

Page 197: ...0 to 3 7 12 DMA Transfer Completion 7 12 1 DMA transfer end interrupt When DMA transfer ends and the TCn bit of the DCHCn register is set a DMA transfer end interrupt INTDMAn is issued to the interrup...

Page 198: ...not supported 3 Times related to DMA transfer The overhead before and after DMA transfer and the minimum execution clock for DMA transfer are shown below Internal RAM access 2 clocks 4 Bus arbitration...

Page 199: ...n or by generation of an exception event i e fetching of an illegal opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servici...

Page 200: ...Port Module 9 0110H 00000110H nextPC Interrupt INTTMG00 TMG00IC Time base 0 Overflow Timer G0 10 0120H 00000120H nextPC Interrupt INTTMG01 TMG01IC Time base 1 Overflow Timer G0 11 0130H 00000130H next...

Page 201: ...tPC Interrupt Note 2 INTFC4RX FC4RXIC CAN4 Receive Interrupt FCAN machine 4 40 0300H 00000300H nextPC Interrupt Note 2 INTFC4TX FC4TXIC CAN4 Transmit Interrupt FCAN machine 4 41 0310H 00000310H nextPC...

Page 202: ...t INTDMA2 DMA2IC DMA Channel 2 transfer completed DMA2 54 03E0H 000003E0H nextPC Interrupt INTDMA3 DMA3IC DMA Channel 3 transfer completed DMA3 55 03F0H 000003F0H nextPC Interrupt INTDOVF DOVFIC DMA O...

Page 203: ...I0 is generated while NMI0 is being serviced The new NMI0 request is held pending regardless of the value of the PSW NP bit The pending NMIVC request is acknowledged after servicing of the current NMI...

Page 204: ...EE1V0UM00 Figure 8 1 Example of Non Maskable Interrupt Request Acknowledgement Operation 1 2 a Multiple NMI requests generated at the same time NMI0 and NMIWDT requests generated simultaneously NMI0 a...

Page 205: ...T request generated during NMI0 servicing NP 0 set before NMIWDT request NMIWDT NMI0 request generated during NMIWDT servicing NMI1 request generated during NMIWDT servicing Main routine NMI0 request...

Page 206: ...word FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address corresponding to the non maskable interrupt to the PC and transfers control The processing config...

Page 207: ...ss of the restored PC and PSW Figure 8 3 illustrates how the RETI instruction is processed Figure 8 3 RETI Instruction Processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR ins...

Page 208: ...be read written in 8 bit or 1 bit units Figure 8 5 Interrupt Mode Register 3 INTM3 Notes 1 This register can be written only once ESN0 is cleared to 0 by Reset 2 This register should always be progra...

Page 209: ...rity than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority lev...

Page 210: ...nmasked or when PSW NP 0 and PSW ID 0 as set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing INT input xxIF 1 No xxMK 0 No Is the interrupt mask...

Page 211: ...PSW Figure 8 7 illustrates the processing of the RETI instruction Figure 8 7 RETI Instruction Processing Note For the ISPR register see 8 3 6 In service priority register ISPR on page 220 Caution When...

Page 212: ...ster xxICn When two or more interrupts having the same prior ity level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level alloca...

Page 213: ...quests Main routine EI EI Interrupt request a level 3 Processing of a Processing of b Processing of c Interrupt request c level 3 Processing of d Processing of e EI Interrupt request e level 2 Process...

Page 214: ...terrupt request p level 2 Interrupt request q level 1 Interrupt request r level 0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r...

Page 215: ...fter executing the DI instruction Remark a to c in the figure are the temporary names of interrupt requests shown for the sake of explanation Default priority a b c Main routine EI Interrupt request a...

Page 216: ...Control Registers on page 217 7 6 5 4 3 2 1 0 Address Initial value xxIC xxIF xxMK 0 0 0 xxPR2 xxPR1 xxPR0 FFFFF110H to FFFF18EH 47H Bit Position Bit Name Function 7 xxIF This is an interrupt request...

Page 217: ...0 TMG11PR2 TMG11PR1 TMG11PR0 FFFFF138H GCC10IC GCC10IF GCC10MK 0 0 0 GCC10PR2 GCC10PR1 GCC10PR0 FFFFF13AH GCC11IC GCC11IF GCC11MK 0 0 0 GCC11PR2 GCC11PR1 GCC11PR0 FFFFF13CH GCC12IC GCC12IF GCC12MK 0 0...

Page 218: ...IC SER1IF SER1MK 0 0 0 SER1PR2 SER1PR1 SER1PR0 FFFFF174H SR1IC SR1IF SR1MK 0 0 0 SR1PR2 SR1PR1 SR1PR0 FFFFF176H ST1IC ST1IF ST1MK 0 0 0 ST1PR2 ST1PR1 ST1PR0 FFFFF178H DMA0IC DMA0IF DMA0MK 0 0 0 DMA0PR...

Page 219: ...Remark xx Identification name of each peripheral unit WT TMD P TMG GCC AD MAC FC CSI UART DMA 15 14 13 12 11 10 9 8 Address Initial value IMR0 GCC03MK GCC02MK GCC01MK GCC00MK TMG01MK TMG00MK P5MK P4M...

Page 220: ...igure 8 13 Maskable Interrupt Status Flag ID 7 6 5 4 3 2 1 0 Address Initial value ISPR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 FFFFF19AH 00H Bit Position Bit Name Function 7 to 0 ISPR7 to ISP...

Page 221: ...re equipped with edge detection and need only noise suppression Figure 8 14 Port Interrupt Input Circuit P52 P53 P61 P62 P63 P64 Figure 8 15 Timer G Input Circuit P30 P35 P40 P45 P54 P55 Figure 8 16 N...

Page 222: ...pares the input pin level against a delayed input pin level The filter output follows the filter input if this compare operation matches 8 4 2 Interrupt Trigger Mode Selection The valid edge of the IN...

Page 223: ...value INTM0 ES031 ES030 ES021 ES020 ES011 ES010 ES001 ES000 FFFFF880H 00H Bit Position Bit Name Function 7 6 ES031 ES030 Edge selection for INTP3 to interrupt controller Selects active edge for interr...

Page 224: ...ion 7 6 ES071 ES070 Edge selection for INTP05 to interrupt controller Selects active edge for interrupt generation ES071 ES070 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edg...

Page 225: ...on 7 6 ES111 ES110 Edge selection for INTP21 to interrupt controller Selects active edge for interrupt generation ES111 ES110 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edge...

Page 226: ...onality is masked by PMC60 Selection of valid edge for NMI must be performed while PMC60 is 0 2 Install appropriate interrupt handler for NMI before reprogramming edge detection or port function 7 6 5...

Page 227: ...ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 8 21 illustra...

Page 228: ...trol to the address of the restored PC and PSW Figure 8 22 illustrates the processing of the RETI instruction Figure 8 22 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are...

Page 229: ...e that exception processing is in progress It is set when an exception occurs Figure 8 23 Exception Status Flag EP 31 8 7 6 5 4 3 2 1 0 Initial value PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 230: ...ted when an instruction applicable to this illegal instruction is executed Remark Arbitrary 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to t...

Page 231: ...ction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the r...

Page 232: ...s generated the CPU performs the following processing transfers control to the debug monitor routine and shifts to debug mode 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets th...

Page 233: ...ruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the...

Page 234: ...cessing control is executed when an interrupt has an enable status ID 0 Thus if multiple interrupts are executed it is necessary to have an interrupt enable status ID 0 even for an interrupt processin...

Page 235: ...PPRn0 to PPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt processing that has been suspended as a r...

Page 236: ...rdware STOP mode When an external bus is accessed When there are two or more successive interrupt request non sampling instructions see 8 9 Periods in Which Interrupts Are Not Acknowledged on page 237...

Page 237: ...re as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the interrupt control register PlCn in service priority register ISPR and command register PRCMD...

Page 238: ...238 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 239: ...d Spectrum PLL for CPU BCU clock supply Clock sources Oscillation through oscillator connection Oscillation through sub oscillator connection during sub watch mode Power save modes WATCH mode Sub WATC...

Page 240: ...cture 64 fX 4 MHz 50 fX 5 MHz 1 2 fCPU 1 128 fX fXT fXXP fXX 1 2 SSCG Main System Clock OSC Subsystem Clock OSC XT1 XT2 X1 X2 STOP WATCH S WATCH PLL Circuit 8 STOP WATCH S WATCH Prescaler 8 fXX 6 fXX...

Page 241: ...ation time the software must remain in a loop and the CPU and the peripherals are supplied by the main oscillator clock Switching to an unstable clock source is not protected by hardware SCEN SSCG ena...

Page 242: ...LEN bit and the SCEN bit are allowed to be set 1 when the system remains in the main oscillation mode CPU and peripherals are using the main oscillator as the clock supply To write data to the CKC reg...

Page 243: ...ster can be read in 8 or 1 bit units Figure 9 3 Clock Generator Status Register CGSTAT 7 6 5 4 3 2 1 0 Address Initial value CGSTAT 0 0 0 0 0 0 OSCSTAT SCSTAT FFFFF824H 00H Bit name Function OSCSTAT M...

Page 244: ...he set data to the destination register WCC Remarks 1 If it is required to switch to another WDT clock source it is recommended to monitor the status of the concerned clock source to be selected befor...

Page 245: ...ister can be read or written in 8 bit units Figure 9 5 Processor Clock Control Register PCC 1 2 7 6 5 4 3 2 1 0 Address Initial value PCC FRC 0 MFRC CLS 0 0 CKS1 CKS0 FFFFF828H 00H Bit name Function F...

Page 246: ...t protected by hardware 2 It is only possible to change the contents of the PCC register for one time after the occurrence of a Reset or if a power save mode has been released 3 After release from Wat...

Page 247: ...rce of the last system reset This register can only be read in 8 or 1 bit units Figure 9 6 Reset Source Monitor Register RSM 7 6 5 4 3 2 1 0 Address Initial value RSM 0 0 0 0 0 0 0 RESM FFFFF830H 00 0...

Page 248: ...until the occurrence of a Reset or the release of a power save mode hap pened Afterwards a power save mode has been released one bit is allowed to be changed 7 6 5 4 3 2 1 0 Address Initial value SCFM...

Page 249: ...can only be written if the SSCG enable bit SCEN is cleared 7 6 5 4 3 2 1 0 Address Initial value SCFC0 SCFC07 SCFC06 SCFC05 SCFC04 SCFC03 SCFC02 SCFC01 SCFC00 FFFFF82CH 3FH Bit Position Bit Name Func...

Page 250: ...ution This register can only be written if the SSCG enable bit SCEN is cleared 7 6 5 4 3 2 1 0 Address Initial value SCFC1 SCFC17 SCFC16 SCFC15 SCFC14 SCFC13 SCFC12 SCFC11 SCFC10 FFFFF82EH 40H Bit Pos...

Page 251: ...aving functions These modes can be combined and switched to suit the target application which enables effective implementation of low power systems Table 9 1 Power Saving Modes Overview Remarks 1 Oper...

Page 252: ...Power Save Mode State Transition Diagram Notes 1 The SSCG and PLL is deactivated per hardware 2 Enable SSCG and PLL manual Normal operation mode Software STOP mode Set STOP mode IDLE mode Set IDLE mo...

Page 253: ...provides low power consumption where the power is only consumed from the OSC Main oscillator Sub Oscillator and Watch timer Watchdog timer This mode is entered by set ting registers with software 3 WA...

Page 254: ...n on on on on on on on on on on SSCG off SCEN Note SCEN Note SCEN Note SCEN Note off off off off off off PLL off PLLEN Note PLLEN Note PLLEN Note PLLEN Note off off off off off off CPU clock CLS CKS 0...

Page 255: ...H H H operate RD Hi Z H H H H operate WAIT operate RESOUT LOW HIGH HIGH HIGH HIGH HIGH TIG05 to TIG00 TIG15 to TIG10 TIC01 to TIC00 N A operate INTP05 INTP00 INTP15 INTP10 INTP21 INTP20 INTP5 to INTP...

Page 256: ...d maskable inter rupt request or RESET signal input 1 Release by interrupt request The HALT mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level...

Page 257: ...ed interrupt request with a higher priority than the previous one is subsequently generated the program branches to the vector address for the latter interrupt 2 Release by RESET pin input This operat...

Page 258: ...Table 9 6 Operating States in IDLE Mode IDLE mode release Release operation is same as release from HALT mode The IDLE mode is released by NMI RESET signal input or an unmasked maskable interrupt req...

Page 259: ...or RESET signal input 1 Release by interrupt request The WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level After oscillator stabilizati...

Page 260: ...ion Remark Before entering the WATCH mode the SSCG and PLL are switched off by hardware After the WATCH mode has been released the SSCG and PLL can be switched on by software once However the start up...

Page 261: ...stopped but the contents of all registers and internal RAM prior to entering this mode are retained On chip other peripheral hardware operation is also stopped The state of the various hardware units...

Page 262: ...errupt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non maskable one priorities than the currently serviced interrupt request is generated the int...

Page 263: ...set operation The Oscillator stabilization time must be ensured by reset input Figure 9 11 Sub Watch mode released by RESET input Main Oscillation circuit stop Sub Watch mode setting Main Oscillation...

Page 264: ...leased the PLL can be switched on by soft ware again once However the start up of the PLL causes always a certain delay of some Milliseconds During this time the clock operates but the CPU operation i...

Page 265: ...but the contents of all registers and internal RAM prior to entering this mode are retained V850E CA2 peripherals operations are also stopped except Sub oscillator and Watchdog timer in case of SOSTP...

Page 266: ...e as normal reset operation Oscillator stabilization time must be ensured by reset input Figure 9 13 STOP mode released by RESET input Oscillation circuit stop STOP mode setting Main Oscillation circu...

Page 267: ...PLL can be switched on any software again once However the start up of the SSCG and PLL cause always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is s...

Page 268: ...truction Bit manipulation instruction SET1 CLR1 NOT1 instruction 2 Prepare data in any one of the general purpose registers to set to the specific register 3 Write arbitrary data to the command regist...

Page 269: ...m may result 2 Although the data written to the PHCMD register is dummy data use the same register as the general register used in specific register setting 4 for writing to the PHCMD register 3 The s...

Page 270: ...Main clock oscillator enable control bit 1 Main oscillator remains stopped after sub Watch mode release The CPU will start from sub clock 0 Main oscillator will be enabled after sub Watch mode release...

Page 271: ...bit timer counter that can perform the following operations 2 capture compare register Programmable pulse generator function Interval timer function PWM output External signal cycle measurement sub os...

Page 272: ...enerated by CCC01 match signal Overflow interrupt request 1 source INTTMC0 generated upon overflow of TMC0 register Timer counter count clock sources 1 type internal peripheral clock cycle One of two...

Page 273: ...1 Block Diagram of Timer C Remark fPCLK internal peripheral clock PSM CMODE Sub Clock Calibration TIC00 Edge Detection TIC01 Edge Detection INTWT fPCLK fX 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 R Q S...

Page 274: ...be read If writing is performed to the TMC0 register the subsequent operation is undefined 2 If the CAE bit of the TMCC00 register is cleared to 0 a reset is performed asynchronously TMC0 performs th...

Page 275: ...fPCLK 64 fPCLK 128 and fPCLK 256 by the TMCC00 register Remark fPCLK internal peripheral clock An overflow interrupt can be generated if the timer overflows Caution The count clock cannot be changed w...

Page 276: ...bit and CMS0 bit specifications of Timer C control register 1 TMCC01 These registers can be read written in 16 bit units However write operations can only be performed in compare mode Figure 10 3 Cap...

Page 277: ...tting CCC0n registers to compare registers CMS1 and CMS0 of TMCC01 1 When these registers are set to compare registers the TMC0 and register values are compared for each timer count clock and an inter...

Page 278: ...0 overflow 0 No overflow 1 Overflow The OVF bit becomes 1 when TMC0 changes from FFFFH to 0000H An overflow interrupt request INTTMC0 is generated at the same time However if CCC00 is set to the compa...

Page 279: ...internal peripheral clock 1 CE Controls the operation of TMC0 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution If CE 0 the external pulse output TOC0 beco...

Page 280: ...the flip flop of the TOC0 output Figure 10 6 Timer C control Register 1 TMCC01 1 2 7 6 5 4 3 2 1 0 Address Initial value TMCC01 OST ENTO ALV 0 CCLR 0 CMS1 CMS0 FFFF F608H 20H Bit Position Bit name Fu...

Page 281: ...ration 0 Disable clearing 1 Enable clearing TMC0 is cleared when CCC00 and TMC0 match during com pare operation 1 CMS1 Selects operation mode of capture compare register CCC01 0 Register operates as c...

Page 282: ...nge the bits of SESC0 register during timer operation If they have to be changed they must be changed after setting the CE bit of the TMCC00 register to 0 If the SESC0 register is overwritten during t...

Page 283: ...imer output signal TOC0 can be set or reset Also a capture operation that holds the TMC0 count value in the CCC00 or CCC01 register is performed synchronized with the valid edge that was detected from...

Page 284: ...00H Also the overflow interrupt INTTMC0 is not generated When the TMC0 counter register is changed from FFFFH to 0000H because the CE bit changes from 1 to 0 the TMC0 register is considered to be clea...

Page 285: ...NTCCC00 or INTCCC01 n 0 1 is generated by TICn0 or TICn1 signal input and is used as an external trigger capture trigger The valid edge of the capture trigger is set by valid edge selection register S...

Page 286: ...rising and falling edges are set as capture triggers the input pulse width from an external source can be measured Figure 10 11 Timing of capture for pulse width measurement both edges Remark D0 to D2...

Page 287: ...onding port pins P5 to Timer C input PM5 to input PMC5 to Timer C0 2 set CAE bit of TMCC00 register to 1 for activating the Timer C peripheral 3 set the valid edge of the TICn0 pin with the IES01 and...

Page 288: ...Dx that was captured in the CCC01 register according to the x th valid edge input of the TIC01 pin and the TMC0 register s count value D x 1 that was captured in the CCC01 register according to the x...

Page 289: ...compare operation that compares the value that was set in the compare register and the TMC0 count value is performed If the TMC0 count value matches the value of the compare register which had been s...

Page 290: ...e value that was set in advance in the CCC00 register as the interval Setting method 1 set corresponding port pins P5 to Timer C input PM5 to input PMC5 to Timer C0 2 set CAE bit to 1 for activate the...

Page 291: ...TOC0 pin is reset The output level set reset depends on the settings of the ALV and ENTO bits of the TMCC01 register Table 10 2 TOC0 Output Control Figure 10 15 Timing of PWM output operation overview...

Page 292: ...ation 1 When the counter value of the TMC0 register matches the setting value of the CCC00 register the TOC0 output becomes active 2 When the counter value of the TMC0 register matches the setting val...

Page 293: ...between the peripheral macro clock prescaler output and direct clock from the main oscillator input In the Jupiter device the Timer C0 will be used to meas ure the sub clock frequency by capture oper...

Page 294: ...n calibration feature in Jupiter clock controller by setting the CMODE bit in the PSM register to 1 3 Enable Timer C0 and set CCC01 to capture mode 4 On the next watch timer wake up interrupt the capt...

Page 295: ...n the analog noise elimination time two cycles of the input clock 4 The operation of an interrupt output INTCCC00 or INTCCC01 is automatically determined according to the operating state of the captur...

Page 296: ...s can be selected related to the internal peripheral clock fPCLK The range is from fPCLK 2 to fPCLK 256 Interrupt request sources 1 Compare match interrupt INTTMDn generated with CMDn match signal Tim...

Page 297: ...Dn Configuration List n 0 1 Remarks 1 fPCLK Internal peripheral clock 2 S R Set Reset Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output S R Other Functions Timer D...

Page 298: ...ormed asynchronously 2 If the CE bit of the TMCDn register is cleared to 0 a reset is performed synchronized with the internal clock Similarly a synchronized reset is performed after a match with the...

Page 299: ...r side is read out CMDn can be read written in 16 bit units Figure 10 20 Timer Dn Compare Register CMDn n 0 1 Cautions 1 A write operation to the a CMDn register requires fPCLK 2 clocks until the valu...

Page 300: ...l U15839EE1V0UM00 Figure 10 21 Timing of Timer Dn Operation a When TMDn CMDn b When TMDn CMDn Remarks 1 p TMDn value when overwritten 2 q CMDn value when overwritten 3 n 0 1 TMDn CAE CE CMDn INTTMDn q...

Page 301: ...change the CS2 to CS0 bits during timer operation If they are to be changed they must be changed after setting the CE bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operat...

Page 302: ...be cleared to 0 at the next count timing This function enables Timer Dn to be used as an interval timer CMDn can also be set to 0 In this case when an overflow occurs and TMDn becomes 0 a match is de...

Page 303: ...ser s Manual U15839EE1V0UM00 Figure 10 23 Timing of Compare Operation 2 2 b When CMDn is set to 0 Remark Interval time FFFFH 2 Count clock cycle 1 0 0 0 FFFFH Overflow TMDn CMDn TMDn clear Match detec...

Page 304: ...refer to Figure 10 23 Timing of Com pare Operation 1 2 on page 302 The setup procedure is shown below n 0 1 1 Set the CAE bit to 1 2 Set each register Select the count clock using the CS2 to CS0 bits...

Page 305: ...the CMDn register is transferred to internal units When writing continuously to the CMDn register be sure to secure a time interval of at least fPCLK 2 clocks 5 The CMDn register can be overwritten o...

Page 306: ...se interval and frequency measurement counter event counter Interval timer Programmable pulse output PWM output timer Remark In this Timer Gn chapter following indexes were consequently used m 1 to 4...

Page 307: ...verflow interrupt requests 2 types In free run mode the INTTMGn0 INTTMGn1 interrupt is generated when the count value of TMGn0 TMGn1 toggles from FFFFH to 0000H In match and clear mode the INTTMGn0 IN...

Page 308: ...n5 INTCCGn0 INTCCGn1 INTCCGn2 INTCCGn3 INTCCGn4 INTCCGn5 TOGn1 Clear TOGn3 TOGn4 Clear Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Eliminat...

Page 309: ...ipheral clock 2 n 0 1 Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output PWM Timer Gn fPCLK fPCLK 2 fPCLK 4 fPCLK 8 fPCLK 16 fPCLK 32 fPCLK 64 fPCLK 128 TMGn0 R INT...

Page 310: ...ers GCCn0 GCCn5 Counter clear can be set by software Counter stop can be set by software These registers can be read in 16 bit units Figure 10 25 Timer Gn Counter 0 Value Registers TMGn0 Figure 10 26...

Page 311: ...and clear mode is used to reduce the number of valid bits of the counter TMGn0 TMGn1 These registers can be read written in 16 bit units Caution If in Compare Mode write to this registers before POWE...

Page 312: ...compare value and the TOGnm Output m 1 to 4 can generate a PWW if they are activated These registers can be read written in 16 bit units Figure 10 29 Timer Gn free assignable Capture Compare Registers...

Page 313: ...ter are cleared the TOGnm pins m 1 to 4 are inactive all the time 1 operation enable Remark At least 7 peripheral clocks fPCLK are need to start the timer function 14 OLDE Set Output Delay Operation 0...

Page 314: ...nter is cleared and the interrupt INTCCGn5 INTCCGn0 occurs Caution When the POWER bit is set the rewriting of this Bits are prohibited Simultaneously writing with the POWER bit is allowed 3 1 CLRGx Sp...

Page 315: ...0 1 This register is the high byte of the TMGMn register This register can be read written in 8 bit or 1 bit units Figure 10 32 Timer Gn Mode Register Low TMGMnH The explanation of the bit 7 to 0 is t...

Page 316: ...IEG11 IEG10 IEG01 IEG00 FFFF 642H 0000H TMGCM1H TBG4 TBG3 TBG2 TBG1 IEG51 IEG50 IEG41 IEG40 IEG31 IEG30 IEG21 IEG20 IEG11 IEG10 IEG01 IEG00 FFFF 682H 0000H Bit Position Bit Name Function 15 to 12 TBGm...

Page 317: ...his register is the high byte of the TMGCMnH register This register can be read written in 8 bit or 1 bit units Figure 10 35 Timer Gn Channel Mode Register TMGCMnH The explanation of the bit 7 to 0 is...

Page 318: ...CTLG1H SWFG4 ALVG4 CCSG4 0 SWFG3 ALVG3 CCSG3 0 SWFG2 ALVG2 CCSG2 0 SWFG1 ALVG1 CCSG1 0 FFFF F684H 4444H Bit Position Bit Name Function 15 11 7 3 SWFGm Fixes the TOGnm pin output level according to the...

Page 319: ...High OCTLGnH This register is the low byte of the OCTLGnH register This register can be read written in 8 bit or 1 bit units Figure 10 38 Timer Gn Output Control Register High OCTLGnH The explanation...

Page 320: ...ddress Initial value TMGST0 ENFG1 ENFG2 CCFG5 CCFG4 CCFG3 CCFG2 CCFG1 CCFG0 FFFF F646H 00H TMGST1 ENFG1 ENFG2 CCFG5 CCFG4 CCFG3 CCFG2 CCFG1 CCFG0 FFFF F686H 00H Bit Position Bit Name Function 5 to 0 C...

Page 321: ...where the count clock is set to fPCLK 2 However 0FFFH is set in GCCn0 Similar delays are added also when a transition is made from the active to inactive level So a relative pulse width is guaranteed...

Page 322: ...erated only when the value of the GCCn0 register is FFFFH 2 An interrupt is generated only when the value of the GCCn0 register is not FFFFH Remark The setting of the CCSGm bit in combination with the...

Page 323: ...e values In compare mode the new compare value will be immediately active In PWM mode the new compare value will be active first after the next overflow or match clear of the assigned counter TMG0 TMG...

Page 324: ...ting up from 0000H to FFFFH generates an overflow and start again In the match and clear mode which is described in Chapter 10 3 8 on page 335 the fixed assigned register GCCn0 GCCn5 is used to reduce...

Page 325: ...is stored in GCCny and an edge detection interrupt INTCCGny is output 2 When the counter overflows an overflow interrupt INTTMGn0 or INTTMGn1 is generated 3 If an overflow has occurred between capture...

Page 326: ...itry 3 to 4 periods of the count up signal are required from the input of a waveform to TIGn0 until a capture interrupt is output See Chapter 10 1 3 Basic configuration 1 16 bit counter TMC0 b Synchro...

Page 327: ...unt clock are required from edge input until an interrupt signal is output and capture operation is performed The timing chart is shown below Basic settings x 0 1 and y 0 to 5 Figure 10 42 Timing of c...

Page 328: ...masking is performed to prevent the initial TIGny level from being recognized as an edge by mistake The timing chart for starting edge detection is shown below Basic settings x 0 1 and y 0 to 5 Figure...

Page 329: ...Gn0 register 3 Write data to GCCnm 4 Start timer operation by setting POWER and TMG0E or TMG1E Compare Operation 1 When the value of the counter matches the value of GCCnm m 0 to 4 a match interrupt I...

Page 330: ...and INTTMGn0 INTTMGn1 are activated when the value of the counter changes from FFFFH to 0000H d When GCCnm is rewritten during operation When GCCn1 is rewritten from 5555H to AAAAH TMGn0 is selected...

Page 331: ...CSE02 to CSE00 bits TMGn0 register 3 Specify the active level of a timer output TOGnm pin with the ALVGm bit 4 When using multiple timer outputs the user can prevent TOGnm from becoming active simulta...

Page 332: ...ansition until the next overflow occurs After the first overflow occurs TOGnm is activated 4 When the value of the counter matches the value of GCCnm TOGnm is deactivated and a match interrupt INTCCGn...

Page 333: ...FFFFH is set in GCCnm m 1 to 4 When FFFFH is set in GCCnm TOGnm outputs the inactive level for one clock period immediately after each counter overflow except the first overflow The figure shows the...

Page 334: ...eration free run GCCn1 and TMGn0 are selected If GCCn1 is rewritten to AAAAH after the second INTCCGn1 is generated as shown in the figure above AAAAH is reloaded to the GCCn1 register when the next o...

Page 335: ...cycle with the CSE12 to CSE10 TMGn1 bits or CSE02 to CSE00 TMGn0 bits 3 Select a valid TIGm edge with the IEGm1 and IEGm0 bit A rising edge falling edge or both edges can be selected 4 Set an upper l...

Page 336: ...page 327 Caution If two or more match and clear events occur between captures a software based measure needs to be taken to count INTCCGn0 or INTCCGn5 c When 0000H is set in GCCn0 or GCCn5 match and c...

Page 337: ...of the counter in GCCn0 or GCCn5 4 Write data to GCCnm 5 Start timer operation by setting the POWER bit and TMGxE bit x 0 1 Operation 1 When the value of the counter matches the value of GCCnm a matc...

Page 338: ...s set in GCCn0 or GCCn5 match and clear When FFFFH is set in GCCn0 or GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGn0 or INTTMGn1 is generated but INTCCGn...

Page 339: ...Gn0 is selected as the counter and 0FFFH is set in GCCn0 Figure 10 52 Timing when GCCnm is rewritten during operation match and clear Caution To perform successive write access during operation for re...

Page 340: ...MGn0 bits 3 Specify the active level of a timer output TOGnm with the ALVGm bit 4 When using multiple timer outputs the user can prevent TOGnm from making transitions simultaneously by setting the OLD...

Page 341: ...nt 5 When the value of the counter matches the value of GCCnm TOGnm makes a transition to the inactive level and a match interrupt INTCCGnm is output 6 When the next match and clear event occurs INTCC...

Page 342: ...nerated but INTCCGn0 INTCCGn5 is not generated b When 0000H is set in GCCnm match and clear When 0000H is set in GCCnm TOGnm is tied to the inactive level The figure below shows the state of TOGn1 whe...

Page 343: ...inactive level for only one clock period immediately after each match and clear event excluding the first match and clear event The figure below shows the state of TOGn1 when 0FFFH is set in GCCn0 an...

Page 344: ...m TOGnm starts and continues outputting the active level immediately after the first match and clear event until count operation stops The figure shows the state of TOGn1 when 0FFFH is set in GCCn0 1F...

Page 345: ...GCCnm is rewritten during operation match and clear If GCCn1 is rewritten to 0AAAH after the second INTCCGn1 is generated as shown in the figure above 0AAAH is reloaded to the GCCn1 register when the...

Page 346: ...ding on the timing This is because the count up signal of the counter is used for sampling timing The upper figure below shows the timing chart for performing edge detection The lower figure below sho...

Page 347: ...level of the TOGnm pins m 1 to 4 When in compare mode the rewriting of the GCCn0 or GCCn5 register is prohibited In compare mode these registers set the value for the match and clear mode of the TMGn...

Page 348: ...er than POWER bit than the Timer Gn needs 4 peripheral clocks periods fPCLK to start counting When a capture register GCCny is read the capturing is disable during read operation This is intended to p...

Page 349: ...watch timer generates an interrupt request INTWT at time intervals of 500 s to 16 4 s by using the clock selector for the Watch Timer see Chapter 8 2 Configuration on page 198 2 Interval timer The in...

Page 350: ...of the 5 bit counter and sets the set time of the watch flag WTM is set by a 1 bit or 8 bit memory manipulation instruction Figure 11 2 Watch Timer Mode Control Register WTM 1 2 Item Configuration Cou...

Page 351: ...TM 2 2 Remark fW Watch timer clock frequency WTM3 WTM2 Selects Set Time of Watch Flag 0 0 214 fW 0 1 213 fW 1 0 25 fW 1 1 24 fW WTM1 Controls Operation of 5 bit Counter 0 Clears after operation stops...

Page 352: ...the Watch Timer With the WTSELn bits n 0 1 of the CKC register 6 different clocks can be switched as the Watch Timer clock Table 11 2 Selection of the Watch Timer Clock Note WTSEL1 bit of CKC registe...

Page 353: ...the watch timer mode control register WTM are set to 1 The WTM0 bit has to be set to 1 either it was 1 before In that case the frequency of the running 11 bit prescaler is not influenced The 5 bit wa...

Page 354: ...val of the Watch Timer The interval time can be selected by the WTM4 through WTM6 bits of the watch timer mode control register WTM Table 11 4 Example for Interval Time of Interval Timer Remarks 1 fX...

Page 355: ...CKC register Clock Generator and the WTM Watch Timer register Remarks 1 fW Watch timer clock frequency 2 n Interval timer operation numbers Start 5 bit counter Overflow Overflow 0H Interrupt time of w...

Page 356: ...356 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 357: ...Remark fWD Watchdog Timer clock frequency depends on clock tree settings 1 Interrupt mode This mode detects program runaway When runaway is detected a non maskable interrupt can be generated 2 RESET m...

Page 358: ...ion The watchdog timer consists of the following hardware Table 12 1 Watchdog Timer Configuration Item Configuration Control registers Watchdog timer clock selection register WDCS Watchdog timer mode...

Page 359: ...truction Figure 12 2 Watchdog Timer Clock Selection Register WDCS Note This are only 2 examples for fWD The clock depends on the clock tree settings and the external main oscillator resonators 4 or 5...

Page 360: ...egister cannot be cleared to 0 by software Therefore when the count starts the count cannot be stopped except by RESET input 2 The WDTM4 bit has to set to 1 at the initialisation of the WDT Cautions 1...

Page 361: ...mer Mode Register WCMD 4 Watchdog timer command status register WPHS The WPHS register monitors the success of a write instruction to the WDTM register If the write to WDTM fails because of violating...

Page 362: ...tchdog timer when operating the HALT mode since the watchdog timer is running in HALT mode For details of the possible time settings please refer to Figure 12 2 Watchdog Timer Clock Selec tion Registe...

Page 363: ...s Clocked serial interfaces CSI00 to CSI02 3 channels FCAN controller 4 channels Remark For details about the FCAN controller refer to Chapter 13 FCAN Interface Function UART50 and UART51 transmit rec...

Page 364: ...r Framing error Overrun error Interrupt sources 3 types Reception error interrupt INTSERn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion...

Page 365: ...h indicates the hold status of TXBn data and the transmission shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is con...

Page 366: ...ol parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn register...

Page 367: ...ration clock stops fixed to low level and an asynchronous reset is applied to internal UART5n latch The TXDn pin output is low level when the Power bit 0 and high level when the Power bit 1 Therefore...

Page 368: ...ay not be successful For details about the base clock refer to 13 2 6 Dedicated baud rate generators BRG of UART5n n 0 1 on page 384 4 3 PS1 PS0 Controls parity bit PS1 PS0 Transmit Operation Receive...

Page 369: ...bits 1 8 bits Caution To overwrite the CL bit first clear 0 the TXE and RXE bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Caution To overwrite the SL bit first clear 0 the TXE...

Page 370: ...egisters ASIS0 ASIS1 7 6 5 4 3 2 1 0 Address Initial value ASIS0 0 0 0 0 0 PE FE OVE FFFF FA03H 00H ASIS1 0 0 0 0 0 PE FE OVE FFFF FA43H 00H Bit Position Bit Name Function 2 PE This is a status flag t...

Page 371: ...cannot be guaranteed when data is written to TXBn register 7 6 5 4 3 2 1 0 Address Initial value ASIF0 0 0 0 0 0 0 TXBF0 TXSF0 FFFF FA05H 00H ASIF1 0 0 0 0 0 0 TXBF0 TXSF0 FFFF FA45H 00H Bit Position...

Page 372: ...n register are retained and no processing is performed for transferring data to the RXBn register even when the shift in processing of one frame is completed Also no reception completion interrupt is...

Page 373: ...nd a transmission completion interrupt request INTSTn is generated synchronized with the completion of the transmission of one frame from the transmission shift register For information about the timi...

Page 374: ...a reception completion interrupt INTSRn is generated when an error occurs can be specified according to the ISRM bit of the ASIMn register When reception is disabled no reception error interrupt is g...

Page 375: ...in Figure 13 7 The character bit length within one data frame the type of parity and the stop bit length are specified according to the asynchronous serial interface mode register ASIMn n 0 1 Also dat...

Page 376: ...ansmission shift register outputs data to the TXD5n pin the transmit data is transferred sequential starting with the start bit The start bit parity bit and stop bits are added automatically c Transmi...

Page 377: ...the transmission status and whether or not data can be written to the TXBn register n 0 1 Caution Transmit data should be written when the TXBF bit is 0 The transmission unit should be initialized whe...

Page 378: ...te start bit Start data 1 transmissionNote 0 1 4 Read ASIFn register confirm that TXBF bit 0 Write data 2 1 1 Transmission in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read AS...

Page 379: ...on in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read ASIFn register confirm that TXSF bit 1 There is no write data 7 Generate start bit Start data n transmission Transmission...

Page 380: ...1 c Reception completion interrupt When RXE bit 1 in the ASIMn register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSRn is generat...

Page 381: ...INTSERn interrupt by clearing the ISRM bit of the ASIMn register to 0 Figure 13 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 a No error occurs during reception b An...

Page 382: ...number is odd b Odd parity During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is...

Page 383: ...s not delivered to the internal circuit see Figure 12 15 Refer to 12 2 6 1 a Basic clock Clock regarding the basic clock Also since the circuit is configured as shown in Figure 12 14 internal processi...

Page 384: ...ception 1 Baud rate generator configuration Figure 13 16 Baud Rate Generator BRG Configuration of UART5n n 0 1 Remark n 0 1 a Basic clock Clock When Power bit 1 in the ASIMn register the clock selecte...

Page 385: ...the TPS3 to TPS0 bits becomes the basic clock Clock of the transmission reception module Its frequency is referred to as fCLK This register can be read or written in 8 bit or 1 bit units Figure 13 17...

Page 386: ...to TPS3 to TPS0 bits of CKSRm register 2 k Value set according to MDL7 to MDL0 bits k 8 9 10 255 3 The baud rate is the output clock for the 8 bit counter divided by 2 4 x don t care 7 6 5 4 3 2 1 0 A...

Page 387: ...1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable...

Page 388: ...6 fPCLK 128 104 0 16 fPCLK 32 130 0 16 fPCLK 32 104 0 16 1200 fPCLK 64 130 0 16 fPCLK 64 104 0 16 fPCLK 16 130 0 16 fPCLK 16 104 0 16 2400 fPCLK 32 130 0 16 fPCLK 32 104 0 16 fPCLK 8 130 0 16 fPCLK 8...

Page 389: ...re 13 19 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGCm register If all data up to the final data stop bit is in time fo...

Page 390: ...n can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 13 5 Maximum and Minimum Allowable Baud Rate Error Remarks 1 The receptio...

Page 391: ...Therefore the transfer rate during continuous transmission is as follows 13 2 7 Precautions When the supply of clocks to UART5n n 0 1 is stopped for example IDLE or STOP mode operation stops with eac...

Page 392: ...t Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SO0n Serial transmit data output SI0n Serial transmit data input SCK0n Serial clock input output Interrupt sources 1...

Page 393: ...ual transmission reception operations are started up by access of the buffer register 5 Clocked serial interface reception buffer registers SIRB0 to SIRB2 The SIRBn register is a 16 bit buffer registe...

Page 394: ...r Counts the serial clock output or input during transmission reception operation and checks whether 8 bit data transmission reception has been performed 16 Interrupt control circuit Controls the inte...

Page 395: ...IE bit to 0 For the SCK0n and SO0n pin output status when the CSIE bit 0 refer to 13 3 5 Output pins on page 422 6 TRMD Specifies transmission reception mode 0 Receive only mode 1 Transmission recepti...

Page 396: ...Initial value CSIC0 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD01H 00H CSIC1 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD41H 00H CSIC2 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD81H 00H Bit Position Bit Name Function 4 3...

Page 397: ...e CSIMn register 0 Bit Position Bit Name Function 2 to 0 CKS2 to CKS0 Specifies input clock CKS2 CKS1 CKS0 Input Clock Mode 0 0 0 fPCLK 4 Master mode 0 0 1 Internal BRG Channel 0 Master mode 0 1 0 Int...

Page 398: ...he SIRBn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform read operation only in the...

Page 399: ...e lower bytes of the SIRBn register Figure 13 25 Clocked Serial Interface Reception Buffer Registers Low SIRBL0 to SIRBL2 Cautions 1 Read the SIRBLn register only when the 8 bit data length has been s...

Page 400: ...gisters SIRBE0 to SIRBE2 Cautions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit o...

Page 401: ...d to read the contents of the SIRBLn register Figure 13 27 Clocked Serial Interface Read Only Reception Buffer Registers Low SIRBEL0 to SIRBEL1 Cautions 1 The receive operation is not started even if...

Page 402: ...ngle transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guar...

Page 403: ...Clocked Serial Interface Transmission Buffer Registers Low SOTBL0 to SOTBL2 Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the s...

Page 404: ...gth has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 1...

Page 405: ...Clocked Serial Interface Initial Transmission Buffer Registers Low SOTBFL0 to SOTBFL2 Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIM0 register 0 and...

Page 406: ...gister only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data...

Page 407: ...the lower bytes of the SIOn register Figure 13 33 Serial I O Shift Registers Low SIOL0 to SIOL2 Caution Access the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register...

Page 408: ...ed the value of the CSOT bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSI0n is set 1 and the CSOT bit i...

Page 409: ...ation mode CKP bit 0 DAP bit 0 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn writ...

Page 410: ...n mode CKP bit 0 DAP bit 1 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write wa...

Page 411: ...al delay control CSIT bit of CSIMn register 0 Figure 13 35 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 b When CKP bit 1 DAP bit 0 Remarks 1 n 0 to 2 2 Reg_R W Intern...

Page 412: ...ernal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3...

Page 413: ...not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 13 36 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 Remar...

Page 414: ...en CKP bit 1 DAP bit 1 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was pe...

Page 415: ...by reading the SIOn register Figure 13 37 Repeat Transfer Receive Only Timing Chart Remarks 1 n 0 to 2 2 Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn...

Page 416: ...ompletion interrupt request INTCSI0n 5 When the transmission reception completion interrupt request INTCSI0n has been set to 1 write the next data to the SOTBn register reserve next transfer and read...

Page 417: ...on completion interrupt request INTCSI0n transfer is continued if the SOTBn register can be written within the next transfer reservation period If the SOTBn register cannot be written transfer ends an...

Page 418: ...pared with the period shown in Figure 13 39 Figure 13 39 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 b When data length 16 bits op...

Page 419: ...Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 d When data length 16 bits operation mode CKP bit 0 DAP bit 1 Remark n 0 to 2 SCK0n input output INTCSIn in...

Page 420: ...rs In case of contention between transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and no...

Page 421: ...results refer to Figure 13 41 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 13 41 Interrupt Request and Register Access Contentio...

Page 422: ...1 When any of bits TRMD CCL DIR AUTO and CSICn of the CSIMn register or DAP bit of the CSICn register is overwritten the SO0n pin output changes 2 SOTBm Bit m of SOTBn register m 0 7 15 3 SOTBFm Bit m...

Page 423: ...ers CSIC0 and CSIC1 refer to 12 3 3 2 Clocked serial interface clock selection registers 0 1 CSIC0 CSIC1 If the dedicated baud rate generator output is specified BRG0 or BRG1 respectively is selected...

Page 424: ...8 bit or 1 bit units n 0 to 2 Figure 13 43 Prescaler Mode Registers 0 1 PRSM0 PRSM1 Cautions 1 Do not change the value of the BGCS1 BGCS0 bits during transmission reception operation 2 Set the PRSMn r...

Page 425: ...ntents of the PRSCMn register are overwritten when the value of the CE bit is 1 the cycle of the baud rate signal is not guaranteed d Baud rate signal cycle The baud rate signal cycle is calculated as...

Page 426: ...below the minimum value of 200 ns of the SCK0n cycle tCYSK1 prescribed in the electrical specifications BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 1 4000000 0 0 2 2000000 0 0 4 1000000 0 0 8 50000...

Page 427: ...messages BasicCAN channels 4 masks per CAN module each mask can be assigned to each message Buffered reception FIFO Message buffers can be redefined in normal operation mode FCAN interface and CPU sh...

Page 428: ...vide no memory for the necessary data buffers rather all CAN mod ules have access to the common CAN memory area via a memory access controller MAC The MAC allows integration of machines other than CAN...

Page 429: ...he BPC register 3 The memory area of the FCAN system is divided into certain functional sections The start and end addresses of those sections are given as an address offset value Caution Before acces...

Page 430: ...rite accesses by CPU while the FCAN system is active 1 CAN message buffer section The message buffer section consists of 32 message buffers Each message buffer allocates 32 bytes The message buffers a...

Page 431: ...801H M_EVTm1 Message event register 1Note 3 R W m 20H 802H M_EVTm2 Message event register 2Note 3 m 20H 803H M_EVTm3 Message event register 3Note 3 484 R W m 20H 804H M_DLCm Message data length code r...

Page 432: ...ffective address PP_BASE address offset Address OffsetNote Symbol Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 1004H CCINTP CAN interrupt pending register 467 R 1020H CGINTP CAN global i...

Page 433: ...Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 1000H CSTOP CAN stop register 454 R W 1010H CGST CAN global status register 457 R W bit set clear function 1012H CGIE CAN global interrupt en...

Page 434: ...MASKL0 CAN1 mask 0 register L 485 R W lower half word 1042H C1MASKH0 CAN1 mask 0 register H R W upper half word 1044H C1MASKL1 CAN1 mask 1 register L R W lower half word 1046H C1MASKH1 CAN1 mask 1 reg...

Page 435: ...half word 108EH C2MASKH3 CAN2 mask 3 register H R W upper half word 1090H C2CTRL CAN2 control register 487 R W bit set clear function 1092H C2DEF CAN2 definition register 492 R W bit set clear functi...

Page 436: ...W upper half word 10D0H C3CTRL CAN3 control register 487 R W bit set clear function 10D2H C3DEF CAN3 definition register 492 R W bit set clear function 10D4H C3LAST CAN3 information register 496 R re...

Page 437: ...W upper half word 1110H C4CTRL CAN4 control register 487 R W bit set clear function 1112H C4DEF CAN4 definition register 492 R W bit set clear function 1114H C4LAST CAN4 information register 496 R re...

Page 438: ...stem is integrated in the FCAN system That functional block is supplied by the global time system clock fGTS which is derived from fMEM The time system prescaler scales fGTS and is controlled by the C...

Page 439: ...analyse which particular interrupt event caused the interrupt request by scanning the interrupt pending flags of a bundled interrupt signal group After the particular interrupt has been identified the...

Page 440: ...ng register C3INTP CAN module 3 interrupt pending register C4INTP CAN module 4 interrupt pending register Additionally the entire interrupt pending flags are summarized in one register the CAN interru...

Page 441: ...message is detected as valid i e if no error was detected until the last but one bit of the end of frame EOF was received The selection of the two trigger options is controlled by the TMR bit in the C...

Page 442: ...OF Remark m 00 to 31 M_DLC m Bus Data 1 Bus Data 2 Bus Data 3 Bus Data 4 Bus Data 5 Bus Data 6 Bus Data 7 Bus Data 8 1 M_DATAm 0 2 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note 3 M_DATAm 0 lower...

Page 443: ...against lower prior messages sent by other nodes at the same time due to arbitration mechanism of CAN protocol and against messages waiting to be transmitted in the same node i e inner pri ority inve...

Page 444: ...user must allocate the 5 higher prior transmit messages to message buffers with a lower address There is no sorting needed among the 5 higher prior message buffer Message Buffer Address OffsetNote1 Me...

Page 445: ...igher prior transmit messages assigned to message buffers with lower address values Message Buffer Address Offset Note 1 Message Buffer Number Message Buffer Link Message Buffer TypeNote 2 Identifier...

Page 446: ...stored in the receive buffer linked to mask 2 but always into the non masked receive buffer Furthermore there is a fixed inner storage rule in case several buffers of the same priority class are link...

Page 447: ...ous message storage As soon the CPU reads one of the message buffer with DN flag set and then clears the DN flag the storing in ascending message buffer number order is interrupted Due to the storage...

Page 448: ...ed by message sorting In the FCAN system each CAN module provides 4 different masks For a receive message buffer assigned to a CAN module one of the 4 masks can be selected when the BasicCAN concept i...

Page 449: ...hen setting the transmit request bit TRQ of the M_STATm register for a message buffer defined as receive message buffer m 00 to 31 Same as for generating a data frame from a transmit message buffer th...

Page 450: ...utomatic remote frame handling activities from the FCAN system The application software must handle the remote frame in the expected way 2 RMDE0 RMDE1 bits as well as ATS bit of M_CTRLm register are s...

Page 451: ...the DN flag in the transmit message buffer No reaction at all Table 14 15 shows the detailed handling reaction upon the reception of a remote frame for a transmit message buffer depending on the sett...

Page 452: ...and PD703129 A1 Registers like above where bit access and direct write operations are prohibited are organized in such a way that all bits allowed for manipulation are located in the lower byte bits...

Page 453: ...ss for better vis ibility of the program code it is recommended to perform only 16 bit write accesses 2 n 0 to 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SE_7 SE_6 SE_5 SE_4 SE_3 SE_2 SE_1 SE_0 CL_7 CL_6...

Page 454: ...for the complete FCAN system The CSTP flag can be used to reduce the power consumption when the FCAN system is set to SLEEP mode and STOP mode to a minimum 0 FCAN system is supplied with clock fMEM 1...

Page 455: ...C0 0 MCS MCP3 MCP2 MCP1 MCP0 1014H 7F05H Bit Position Bit Name Function 15 to 8 CGTS7 to CGTS0 Specifies the 8 bit prescaler compare value for the global time system clock fGTS ref to Fig 9 11 Remark...

Page 456: ...System Clock Bit Position Bit Name Function 3 to 0 MCP3 to MCP0 Specifies the prescaler for the memory access clock fMEM ref to Fig 9 10 MCP3 MCP2 MCP1 MCP0 Prescaler m 1 Memory Clock fMEM fMEM1 m 1...

Page 457: ...ad 1 2 Bit Position Bit Name Function 7 MERR Indicates the error status of the memory access controller MAC 0 No error occurrence 1 At least one error occurred since the flag was cleared last A MAC er...

Page 458: ...fers Note 1 1 Operation of all CAN modules are enabled Temporary buffers can be read only Note 1 Caution To ensure that resetting the CAN modules do not cause any unex pected behaviour on the CAN bus...

Page 459: ...EVM bit 8 0 ST_GOM CL_GOM Sets clears the GOM bit 7 CL_MERR Clears the MERR bit 0 No change of MERR bit 1 MERR bit is cleared 0 ST_EFSD CL_EFSD Status of EFSD Bit 0 1 EFSD bit is cleared 0 1 0 EFSD bi...

Page 460: ...Enables interrupt by CAN bridge 0 Interrupt disabled 1 Interrupt enabled Remark Due to the reason that no CAN bridge is implemented in the V850E CA2 device this bit must not be set at any time 2 G_IE2...

Page 461: ...2 Sets clears the G_IE2 bit 9 1 ST_G_IE1 CL_G_IE1 Sets clears the G_IE1 bit ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit 0 1 G_IE7 bit is cleared 0 1 0 G_IE7 bit is set 1 Others No change in G_IE7 bit value...

Page 462: ...lows timer event 0 fGTS 210 timer event 1 fGTS 212 timer event 2 fGTS 214 timer event 3 fGTS 216 Figure 14 15 CAN Global Time System Counter and event generation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 463: ...er can be read and writtenNote 1 in 16 bit units only Figure 14 16 CAN Global Time System Counter CGTSC Notes 1 When writing is performed to CGTSC register the counter is cleared to 0 2 The register a...

Page 464: ...RDY of the M_STATm registers 0 Do not check status of TRQ flag and RDY flag 1 TRQ flag and RDY flag must be set 12 CMSK Search criteria for the mask link bits MT2 to MT0 of the M_CONFm registers 0 Do...

Page 465: ...function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote1 Initial value CGMSR 0 0 0 0 0 0 MM AM 0Note3 0Note3 MFND5 MFND4 MFND3 MFND2 MFND1 MFND0 101AH 0000H Bit Position Bit Name Function 9...

Page 466: ...ansceiver bus harness etc 3 x 1 to 4 Note CAN module 3 and CAN module 4 are available in the derivatives PD703129 A and PD703129 A1 only Caution The internal test bus must only be used when none of th...

Page 467: ...dedicated interrupt pending registers CGINTP C1INTP C2INTP and C3INTP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value CCINTPH 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN4ERR CAN4REC CAN4TR...

Page 468: ...0 0 0 0 CL_ GINT7 0 0 0 CL_ GINT3 CL_ GINT2 CL_ GINT1 0 1020H Read Bit Position Bit Name Function 7 GINT7 Indicates an interrupt of the CAN bridge ELISA GINT7 bit of CGINTP register 0 No Interrupt pe...

Page 469: ...ared by software in the interrupt service routine Caution In case the interrupt pending bit is not cleared by software in the interrupt service routine no subsequent interrupt is generated anymore Wri...

Page 470: ...2INT6 C2INT5 C2INT4 C2INT3 C2INT2 C2INT1 C2INT0 1024H 0000H C3INTP 0 0 0 0 0 0 0 0 0 C3INT6 C3INT5 C3INT4 C3INT3 C3INT2 C3INT1 C3INT0 1026H 0000H C4INTP 0 0 0 0 0 0 0 0 0 C3INT6 C3INT5 C3INT4 C3INT3 C...

Page 471: ...g 1 CxINT1 Indicates a reception completion interrupt of CAN module x 0 No Interrupt pending 1 Interrupt pending 0 CxINT0 Indicates a transmission completion interrupt of CAN module x 0 No Interrupt p...

Page 472: ...D2 3 When received message in standard format mode IDE 0 has less than 18 data bits the values of the not received bits are undefined Remark m 00 to 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Of...

Page 473: ...31 M_CONF00 to M_CONF31 1 2 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_CONFm 0 0 MT2 MT1 MT0 MA2 MA1 MA0 814H m 20H undef Bit Position Bit Name Function 5 to 3 MT2 to MT0 Specifies the messa...

Page 474: ...ell Even the type of the identifier standard or extended and the type of the frame remote or data frame are not respected In normal operation mode the message buffer is not han dled 5 If the message b...

Page 475: ...ast one new message was received Remarks 1 If the DN flag is set for a transmit message buffer it indicates a remote frame reception In case auto answering RMDE0 bit of the M_CTRLm register is active...

Page 476: ...Table 14 16 CAN Message Processing by TRQ and RDY Bits Message Type TRQ RDY Message Processing Any 0 Message buffer is disabled for any processing by the assigned CAN module Receive message 0 1 Messa...

Page 477: ...e Initial value SC_STAT m 0 0 0 0 ST_ ERQ ST_ DN ST_ TRQ ST_ RDY 0 0 0 0 CL_ ERQ CL_ DN CL_ TRQ CL_ RDY 816H m 20H Bit Position Bit Name Function 11 3 ST_ERQ CL_ERQ Sets clears the ERQ bit of the M_ST...

Page 478: ...o 31 1 2 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_DATA m0 D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0 808H m 20H undef M_DATA m1 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 809H m 20H undef M_DATA m...

Page 479: ...time stamp value is sent x 1 to 2 for the derivative PD703128 A x 1 to 4 for the derivatives PD703129 A and PD703129 A1 refer to chapter 14 2 5 Time stamp on page 441 3 When a new message is received...

Page 480: ...Cm register 3 If a DLC is specified to a value greater 8 for a transmit message 8 byte transfer is per formed regardless of the DLC value Remark m 00 to 31 Cautions 1 If a remote frame is received on...

Page 481: ...s and indicates how the DN flag is updated if a remote frame is received on that message buffer For details refer to chapter 14 2 8 Remote frame han dling on page 449 6 RMED0 Specifies the remote fram...

Page 482: ...CAN module might be overwritten by new messages although the DN flag is already set Checking the MOVR bit additionally indicates whether the message buffer has been overwritten 2 R1 Reserved bit valu...

Page 483: ...s calculated according to the following formula effective address PP_BASE address offset Remarks 1 m 00 to 31 2 x 1 to 4 for the derivatives PD703129 A and PD703129 A1 3 x 1 to 2 for the derivative PD...

Page 484: ...ll Message Event Bytes with the value 0x00 at the first initialization and let that initialization unchanged always 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_EVTm0 PTR07 PTR06 PTR05 PTR04 PTR...

Page 485: ...CMIDE Sets the CAN module mask option for the identifier type of the receive message 0 Check identifier type of a received message 1 Do not check identifier type Remark When CMIDE is cleared 0 the sp...

Page 486: ...rivative PD703128 A 3 The register address is calculated according to the following formula effective address PP_BASE address offset SymbolNote1 2 Address OffsetNote 3 x 1 x 2 x 3Note 1 2 x 4Note 1 2...

Page 487: ...050H 0101H C2CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT TPE DLEVR DLEVT OVM TMR STOP SLEEP INIT 1090H 0101H C3CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT TPE DLEVR DLEVT OVM TMR STOP...

Page 488: ...is recessive logical high 3 Data manipulation of the CxSYNC and CxBRP registers is only possi ble during INIT state 4 In INIT state the transmission and reception error counters are cleared and any e...

Page 489: ...ities stopped and set in suspend mode and wake up of the CAN module is only possible by CPU CPU clears STOP bit 1 SLEEP Selects the CAN sleep mode 0 Normal operation mode 1 CAN module sleep mode selec...

Page 490: ...f TPE bit 0 1 TPE bit is cleared 0 1 0 TPE bit is set 1 Others No change in TPE bit value ST_DLEVR CL_DLEVR Status of DLEVR bit 0 1 DLEVR bit is cleared 0 1 0 DLEVR bit is set 1 Others No change in DL...

Page 491: ...effective address PP_BASE address offset Write 2 2 Bit Position Bit Name Function 9 1 ST_SLEEP CL_SLEEP Sets clears the SLEEP bit 8 0 ST_INIT CL_INIT Sets clears the INIT bit ST_SLEEP CL_SLEEP Status...

Page 492: ...0 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 1052H 0000H C2DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 1092H 0000H C3D...

Page 493: ...be used for baud rate detection and diagnos tic purposes Caution When the diagnostic mode MOM 1 is defined for a CAN module the CxBRP register is only accessible in the initialisation state ISTAT 1 Wh...

Page 494: ...ared last Remark For single shot mode SSHT bit 1 this flag indicates a loss of the arbitra tion 2 VALID Indicates valid protocol activity 0 No valid message was detected by the CAN protocol layer 1 At...

Page 495: ...D bit 0 No change of VALID bit 1 VALID bit is cleared 0 1 CL_WAKE Clears the WAKE bit 0 No change of WAKE bit 1 WAKE bit is cleared 0 0 CL_OVR Clears the OVR bit 0 No change of OVR bit 1 OVR bit is cl...

Page 496: ...LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 1094H 00FFH C3LAST 0 0 0 0 LERR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 10D4H 00FFH C4LAST 0 0 0 0 LERR3 L...

Page 497: ...fset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 1056H 0000H C2ERC REC7 REC6 REC5 REC4...

Page 498: ...0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 1058H 0000H C2IE 0 0 0 0 0 0 0 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 1098H 0000H C3IE 0 0 0 0 0 0 0 0 0 E_INT6 E_INT5 E_INT4 E_INT3...

Page 499: ...Interrupt enabled 4 E_INT4 Enables wake up from CAN sleep mode interrupt INT4 0 Interrupt disabled 1 Interrupt enabled 3 E_INT3 Enables interrupt for error passive on reception INT3 0 Interrupt disab...

Page 500: ...it is set 1 Others No change in E_INT6 bit value ST_E_INT5 CL_E_INT5 Status of E_INT5 bit 0 1 E_INT5 bit is cleared 0 1 0 E_INT5 bit is set 1 Others No change in E_INT5 bit value ST_E_INT4 CL_E_INT4 S...

Page 501: ...00FFH C3BA 0 0 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 10DAH 00FFH C4BA 0 0 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 111...

Page 502: ...ction 7 to 0 TMNO7 to TMNO0 Indicates the message buffer which is either waiting to be transmitted or in transmis sion progress TMNO7 to TMNO0 Number of Transmit Message Buffer 0 to 31 Current transmi...

Page 503: ...ion In diagnostic mode the CxBRP register is hidden and the CxDINF register appears instead of it at the same address TLM 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1BRP...

Page 504: ...LM 1 BRP5 to BRP0 TLM 0 Specifies the bit rate prescaler for the CAN protocol layer TLM 0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bit Rate Prescaler fBTL fMEM 2 k 1 k 0 0 0 0 0 0 fBTL fMEM 2 0 0 0 0 0 0 1 fBTL...

Page 505: ...Q for which the CAN module is permitted to lengthen or shorten the phase segments is called synchronisation jump width SJW The SJW value must be less or equal the difference of DBT and SPT which corre...

Page 506: ...SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 105EH 0218H C2SYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 109EH 0218H C3SYNC 0 0 0 SAMP SJWR1 S...

Page 507: ...ster is only possible when the CAN module is set to INIT mode 3 For setting the DBTR and SPTR bits some rules must be observed otherwise the CAN module will malfunction for details refer to chapter 14...

Page 508: ...It is automati cally reset whenever a SOF is detected on the CAN bus Caution In normal operating mode the CxDINF register is hidden and the corresponding CxBRP register appears instead of it at the s...

Page 509: ...ricted to a range from 8 TQ to 25 TQ which corre sponds to the DBTR4 to DBTR0 bits of the CxSYNC register 3 Rule for synchronization jump width SJW setting The number of TQ allowed for soft synchroniz...

Page 510: ...baud rate is calculated The register descriptions show that the prescaler must be an even number between 2 and 128 the data bit time must be a value in the range 8 to 25 As the synchronization jump wi...

Page 511: ...15 data bit time DBT 16 TQ SPTR4 to SPTR0 01100B 12 sampling point SPT 13 TQ or BRP5 to BRP0 000111B 7 prescaler BRP 16 TQ DBTR4 to DBTR0 01011B 11 data bit time DBT 12 TQ SPTR4 to SPTR0 01000B 8 samp...

Page 512: ...PU by sequential accesses to the CAN message buffers the following sequence has to be observed Figure 14 44 Sequential CAN Data Read by CPU As the DN flag is only set by the CAN module and cleared by...

Page 513: ...he message is automatically started whenever the data length code from the M_DLCm register is read by the CPU and the data is copied from the message buffer into the temporary buffer As long as the CP...

Page 514: ...and PD703129 A1 x 1 to 2 for the deriva tive PD703128 A PowerOn RESET or RESET CxCTRL ISTAT 1 INIT 0 CxCTRL ISTAT 0 INIT 1 and CAN bus busy CAN bus idle SLEEP 1and CANbusbusy CxCTRL ISTAT 0 CxCTRL SLE...

Page 515: ...CAN interface Before any operation on the CAN memory can be done it is essential that the common control register are initialised The general initialisation sequence is shown in Figure 14 46 Figure 14...

Page 516: ...ble all CAN modules for i 0 i CAN_MODULES i CAN_ModuleStop i clear GOM flag CGST 0x0001 CGST 0x00FF clear all flags of CGST CGIE 0x00FF disable global interrupts CGCS 0x0000 define internal clock CGTS...

Page 517: ...sed by the sequence according to Figure 14 47 Figure 14 47 Initialisation Sequence for a CAN module Remark x 1 to 4 for the derivatives PD703129 A and PD703129 A1 x 1 to 2 for the deriva tive PD703128...

Page 518: ...CTRL 0x00FE clear CxCTRL except INIT can_mod_ptr CxDEF 0x00FF clear CxDEF can_mod_ptr CxIE 0x00FF clear CxIE can_mod_ptr CxBRP brp_value set CxBRP can_mod_ptr CxSYNC sync_value set CxSYNC can_mod_ptr...

Page 519: ...t There fore the sequence is only required if the CAN module is already in normal operation Figure 14 48 Setting CAN Module into Initialisation State Note In case of permanent bus activity the program...

Page 520: ...unsigned char module_no can_module_type can_mod_ptr define CAN module ptr can_mod_ptr can_module module_no load CAN module ptr if can_mod_ptr CxCTRL 0x0001 0 if INIT flag not yet set can_mod_ptr CxCTR...

Page 521: ...malfunction on the corresponding CAN bus 1 For each CAN module x x 1 to 4 for the derivatives PD703129 A and PD703129 A1 x 1 to 2 for the derivative PD703128 A a Enter sleep mode Set SLEEP bit 1 CxCT...

Page 522: ...522 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 523: ...10 bit resolution on chip A D converter Analog inputs 12 channels Standby function Current cut between AVDD AGND if A D conversion is stopped Current cut between AVREF AGND if A D conversion is stopp...

Page 524: ...put voltage of the D A converter 4 D A converter The D A converter is used to generate a voltage that matches an analog input The output voltage of the D A converter is controlled by the successive ap...

Page 525: ...pin The AVREF pin is used to input reference voltage to the A D converter A signal input to the ANIm pin is converted to a digital signal based on the voltage applied between AVREF and AVSS m 0 to 11...

Page 526: ...bnormal conversion results that are obtained If an A D conversion result from which it is judged that an abnormality occurred in the system is obtained do not perform abnormality processing at once bu...

Page 527: ...gister ADS 15 3 1 Register format of A D Converter Control Register Table 15 2 Register format of A D Converter Control Register SFR name Symbol R W Manipulable Bit Unit After Reset 1 bit 8 bits 16 bi...

Page 528: ...ster ADM Notes 1 The bits FR0 FR1 FR2 and FR3 must not be changed while ADCS bit is set 1 2 Conversion time actual A D conversion time Always set the time to 5 s Conversion time 12 s Caution Be sure n...

Page 529: ...djusted By the selection bits FR3 to FR0 in the ADM register the number of the conversion clocks can be set in the range of 84 to 216 However the settings modifying the conversion time TCONV must keep...

Page 530: ...t The conversion operation restarts from the beginning Figure 15 3 A D Converter Register ADS 7 6 5 4 3 2 1 0 Address Initial value ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0 FFFFF201H 0000H Bit Position Bit Nam...

Page 531: ...ADCRL register is the same as the lower byte of the ADCR register When reading all 8 bits of data of an A D conversion result from the ADCRL register only the higher 2 bits are valid and the lower 6 b...

Page 532: ...nversion The ADCRH register is the same as the higher byte of the ADCR register This register can be read in 1 bit or 8 bit units Figure 15 6 A D Conversion Result Register ADCRH 7 6 5 4 3 2 1 0 Addre...

Page 533: ...ue of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value Port7 Port8 0 0 0 0 P83 ANI11 P82 ANI10 P81...

Page 534: ...units Figure 15 8 Port Function Register 7 PORT7 Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 7 6 5 4 3 2 1 0 Address I...

Page 535: ...he following expression or the following expression where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVDD AVDD pin voltage and A D converter power supply...

Page 536: ...interrupt A D conversion termination interrupt INTAD 1 A D conversion termination interrupt INTAD In A D conversion enabled status an A D conversion termination interrupt is generated when the specifi...

Page 537: ...ut is compared with the voltage generated by the D A converter 3 When the 10 bit comparison is completed the conversion result is stored in the ADCR ADCRL and ADCRH registers and a new conversion oper...

Page 538: ...converter converts one analog input specified in the ADS register The conversion result is stored in the ADCR ADCRL ADCRH register Figure 15 10 No write operation is made to ADM or ADS register durin...

Page 539: ...nput A D conversion ADCR ADCRL ADCRH registers INTAD interrupt Conversion start ADCS bit of ADM register is set 1 ADS3 to ADS0 bits of ADS register are cleared 0 Data 1 Data 2 Data 3 Data 1 Data 2 ANI...

Page 540: ...egisters INTAD interrupt Conversion start ADCS bit of ADM register is set 1 ADS3 to ADS0 bits of ADS register are cleared 0 Data 1 Data 2 Data 1 Data 2 Data 3 Data 4 ANI0 ANI0 ANI1 ANI1 Data 1 Data 3...

Page 541: ...increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 15 13 Analog Input Pin Handling on page 541 to...

Page 542: ...the full scale is expressed by FSR Full Scale Range When the resolution is 10 bits 1LSB 1 210 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by the overall error 2 Overall...

Page 543: ...15 15 Quantization Error 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2 LSB when the digital output changes...

Page 544: ...Error This shows the degree to which the conversion characteristics deviate from the ideal linear rela tionship It expresses the maximum value of the difference between the actual measurement value an...

Page 545: ...EE1V0UM00 Chapter 16 Port Functions 16 1 Features Input Output ports 5 V 51 Input ports 5 V 12 Input Output ports 3 3 V 15 Ports alternate as input output pins of other peripheral functions Input or o...

Page 546: ...ports have 3 3 V power The ports are named ports P1 through P9 and PAH PCM PCT and PCS The configuration is shown below Figure 16 1 Port Configuration Port 2 P20 to P27 Port 3 P30 to P35 Port 4 to P45...

Page 547: ...put output CSI0 CSI1 UART0 A Port 3 P30 to P35 6 bit input output Real time pulse unit RPU input output External interrupt input A Port 4 P40 to P45 6 bit input output Real time pulse unit RPU input o...

Page 548: ...4 Input mode P25 SCKO1 SCKI1 P25 Input mode P26 RXD0 P26 Input mode P27 TXD0 P27 Input mode Port 3 P30 TIG00 INTP00 P30 Input mode PMC3 P31 TOG01 TIG01 P31 Input mode P32 TOG02 TIG02 P32 Input mode P3...

Page 549: ...8 P80 Input ANI8 P81 ANI9 P81 Input ANI9 P82 ANI10 P82 Input ANI10 P83 ANI11 P83 Input ANI11 Port 9 P90 P90 Input mode P91 P91 Input mode P92 P92 Input mode P93 P93 Input mode P94 P94 Input mode P95 P...

Page 550: ...0 Port Name Pin Name Pin Function after Reset Mode Setting Register Port CT PCT0 LWR PCT0 Input mode PMCCT PCT1 UWR PCT1 Input mode PCT4 RD RD Read strobe signal output mode Port CM PCM0 WAIT WAIT Wai...

Page 551: ...e A Block Diagram Remark N 1 to 6 9 Port number n 0 to 7 Port pin for port number 1 2 6 9 n 0 to 6 Port pin for port number 5 n 0 to 3 Port pin for port number 3 4 Peripheral Bus WRPMC Nn PMC Nn WRPM...

Page 552: ...rt Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 3 Type B Block Diagram Remark n 0 to 7 Peripheral Bus WRPMCAHn PMCAHn WRPMAHn PMAHn WRPAHn PAHn RDPAHn Selector Selector Address Select...

Page 553: ...t Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 4 Type C Block Diagram Remark n 0 3 4 Peripheral Bus WRPMCCSn PMCCSn WRPMCSn PMCSn WRPCSn PCSn RDPCSn Selector Selector Address Selector...

Page 554: ...rt Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 5 Type D Block Diagram Remark n 0 1 4 Peripheral Bus WRPMCCTn PMCCTn WRPMCTn PMCTn WRPCTn PCTn RDPCTn Selector Selector Address Selecto...

Page 555: ...pter 16 Port Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 6 Type E Block Diagram Peripheral Bus WRPMCCMn PMCCMn WRPMCMn PMCMn WRPCMn PCMn RDPCMn Selector Selector Address Selector WAI...

Page 556: ...ctioning as a port in control mode it also can operate as the serial interface UART1 FCAN1 FCAN2 FCAN3Note 3 input output 1 Operation in control mode Notes 1 If using peripheral functions the directio...

Page 557: ...t using the port 1 mode control register PMC1 a Port 1 mode register PM1 This register can be read or written in 8 bit or 1 bit units Figure 16 8 Port 1 Mode Register PM1 7 6 5 4 3 2 1 0 Address At Re...

Page 558: ...ut mode 6 PMC16 Specifies operation mode of P16 pin 0 Input output port mode 1 RXD1 input mode 5 PMC15 Specifies operation mode of P15 pin 0 Input output port mode 1 CTXD3 output mode 4 PMC14 Specifie...

Page 559: ...d those values are immediately output Besides functioning as a port in control mode it also can operate as the serial interface UART0 CSI0 CS1 input output Notes 1 If using peripheral functions the di...

Page 560: ...using the port 2 mode control register PMC2 a Port 2 mode register PM2 This register can be read or written in 8 bit or 1 bit units Figure 16 11 Port 2 Mode Register PM2 7 6 5 4 3 2 1 0 Address At Re...

Page 561: ...t mode 6 PMC26 Specifies operation mode of P26 pin 0 Input output port mode 1 RXD0 input mode 5 PMC25 Specifies operation mode of P25 pin 0 Input output port mode 1 SCK1 input output mode 4 PMC24 Spec...

Page 562: ...Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 If using peripheral functions the direction...

Page 563: ...output mode of P2n pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At Reset PMC3 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF444H 00H Bit Position Bit Name F...

Page 564: ...Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 If using peripheral functions the direction...

Page 565: ...output mode of P4n pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At Reset PMC4 0 0 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF446H 00H Bit Position Bit Name F...

Page 566: ...al time pulse unit RPU input output as the serial interface FCAN4Note 3 and as external interrupt request input 1 Operation in control mode Notes 1 If using peripheral functions the direction setting...

Page 567: ...et using the port 5 mode control register PMC5 a Port 5 mode register PM5 This register can be read or written in 8 bit or 1 bit units Figure 16 20 Port 5 Mode Register PM5 7 6 5 4 3 2 1 0 Address At...

Page 568: ...O0 output mode 5 PMC55 Specifies operation mode of P55 pin 0 Input output port mode 1 TI1 input mode or external interrupt request INTP21 input mode 4 PMC54 Specifies operation mode of P54 pin 0 Input...

Page 569: ...ediately output Besides functioning as a port in control mode it also can operate as the serial interface CSI2 or as external interrupt request input Notes 1 If using peripheral functions the directio...

Page 570: ...using the port 6 mode control register PMC6 a Port 6 mode register PM6 This register can be read or written in 8 bit or 1 bit units Figure 16 23 Port 6 Mode Register PM6 7 6 5 4 3 2 1 0 Address At Re...

Page 571: ...65 pin 0 Input output port mode 1 SCK2 input output mode 6 PMC66 Specifies operation mode of P65 pin 0 Input output port mode 1 SO2 output mode 5 PMC65 Specifies operation mode of P65 pin 0 Input outp...

Page 572: ...ailable for port 7 This register can be read in 1 bit or 8 bit units Figure 16 25 Port Function Register 7 P7 Note Reading the digital value of the analog input channel ANIx is disabled during A D con...

Page 573: ...rt Function Register 7 8 P7 P8 Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addres...

Page 574: ...t register and those values are immediately output Note The reset value of register P9 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Settin...

Page 575: ...ster is read the values of PAH are read Writing to the PAH register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can...

Page 576: ...PMCAH This register can be read or written in 8 bit or 1 bit units Figure 16 31 Port AH Mode Control Register PMCAH 7 6 5 4 3 2 1 0 Address At Reset PMAH PMAH7 PMAH6 PMAH5 PMAH4 PMAH3 PMAH2 PMAH1 PMA...

Page 577: ...e immediately output Besides functioning as a port in control mode it also can operate as the chip select signal output when memory is accesses externally Notes 1 If using peripheral functions the dir...

Page 578: ...3 0 0 PMCS0 FFFFF028H 18H Bit Position Bit Name Function 4 PMCS4 Specifies input output mode of PCS4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 3 PMCS3 Specifies input output mo...

Page 579: ...in control mode PCT0 and PCT1 can operate as the write strobe signal outputs when memory is accessed externally PCT4 can also operate as the read strobe signal input Notes 1 If using peripheral functi...

Page 580: ...2AH 03H Bit Position Bit Name Function 4 PMCT4 Specifies input output mode of PCT4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 1 PMCT1 Specifies input output mode of PCT1 pin 0 O...

Page 581: ...ly output Besides functioning as a port in control mode PCM0 can operate as the wait insertion signal input when external slow memory peripherals are connected Notes 1 If using peripheral functions th...

Page 582: ...Register PMCM b Port mode control register PMCCM This register can be read or written in 8 bit or 1 bit units Figure 16 40 Port CM Mode Control Register PMCCM 7 6 5 4 3 2 1 0 Address At Reset PMCM 0...

Page 583: ...s is released and the CPU starts program execution The user has to initialize the contents of various registers as needed within the pro gram 17 2 Features Noise elimination of RESET pin using analog...

Page 584: ...to FCRXD3 only for PD703129 Pin Function RESET D 15 0 Hi Z A 23 0 Hi Z CS 4 3 0 Hi Z WR 1 0 Hi Z RD Hi Z WAIT RESOUT LOW TIG05 to TIG00 TIG15 to TIG10 TIC01 to TIC00 N A INTP05 INTP00 INTP15 INTP10 I...

Page 585: ...cution is started All register will be initialized The RESET pin incorporates a noise eliminator which uses analogue delay to prevent malfunction due to noise 1 Reset signal acknowledgment Figure 17 1...

Page 586: ...has to be applied to the RESET pin This is to secure the clock stabilization time that is necessary after the power is turned on and before a reset signal can be acknowledged Please refer to the Elec...

Page 587: ...into the Reset circuit Oscillation stabilization time is not required after this reset Except WDT reset was triggered in sub watch mode or stop mode This case is handled by the clock controller 17 6 R...

Page 588: ...ng are synchronized On a RESET other than this data is maintained in its previous status On Chip Hardware Register Name Initial Value After Reset CPU Program registers General purpose register r0 0000...

Page 589: ...Instructions are divided into each instruciton group and described This column shows instruction mnemonics This column shows instruction operands refer to Table B 1 This column shows instruction opera...

Page 590: ...lement pointer r30 bit 3 3 bit data for bit number specification imm bit immediate data disp bit displacement regID System register number vector 5 bit data that specifies trap vector number 00H to 1F...

Page 591: ...to bit b of address a saturated n Performs saturated processing of n n is 2 s complements Result of calculation of n If n is n 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n 80000000H as resu...

Page 592: ...NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR Z 1 Not higher Less than or equal H 1011 CY OR Z 0 Higher Greater than N 0...

Page 593: ...adr GR reg1 sign extend disp16 GR reg2 Load memory adr Word SST B reg2 disp7 ep rrrrr0111 ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001 ddddddd Note 1 a...

Page 594: ...1 reg2 rrrrr1110 01RRRRR ddddddddd dddddd1 Note 3 adr GR reg1 sign extend disp16 GR reg2 Load memory adr Word SST B reg2 disp7 ep rrrrr0111 ddddddd adr ep zero extend disp7 Store memory adr GR reg2 By...

Page 595: ...1 1110cccc 00000000 00000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H Saturated operation SAT ADD reg1 reg2 rrrrr000 110RRRRR GR reg2 saturated GR reg2 GR reg1 SAT ADD...

Page 596: ...iiiiiiii GR reg2 GR reg1 XOR zero extend imm16 0 NOT reg1 reg2 rrrrr0000 01RRRRR GR reg2 NOT GR reg1 0 SHL reg1 reg2 rrrrr1111 11RRRRR 000000001 1000000 GR reg2 GR reg2 logically shift left by GR reg1...

Page 597: ...it manip ulate SET1 bit 3 disp16 reg1 00bbb1111 10RRRRR ddddddddd ddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 CLR1 bit 3 disp16 reg1 10bbb1...

Page 598: ...to 0FH 00000050H vector 10H to 1FH RETI 000001111 1100000 000000010 1000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 000001111 1...

Page 599: ...CY OV S Z SAT Notes 1 ddddddd is the higher 7 bits of disp8 2 dddddd is the higher 6 bits of disp8 3 ddddddddddddddd is the higher 15 bits of disp16 4 Only the lower half word data is valid 5 dddddddd...

Page 600: ...600 Preliminary User s Manual U15839EE1V0UM00 MEMO...

Page 601: ...00 to ANI11 49 ASC 132 ASIF0 ASIF1 371 ASIM0 367 ASIM1 367 ASIS0 to ASIS2 370 Asynchronous reset 275 Asynchronous serial interface mode registers 367 Asynchronous serial interface status registers 370...

Page 602: ...ked serial interface mode registers 395 Clocked serial interface read only reception buffer registers 400 Clocked serial interface read only reception buffer registers Low 401 Clocked serial interface...

Page 603: ...transfer mode 189 Transfer end 197 Transfer mode 187 Transfer object 193 Transfer start factors 194 Transfer types 193 Two cycle transfer 193 DMA destination address registers 172 173 DMA disable sta...

Page 604: ...each port 547 Functions of each port pin on reset and registers that set port or control mode 548 G GCCn0 311 GCCn5 311 GCCnm 312 General registers 56 57 general registers 55 57 Global pointer 57 H H...

Page 605: ...INTSER1 374 INTSR0 374 INTSR1 374 INTST0 374 INTST1 374 ISPR 220 L Least Recently Used 155 Link pointer 57 Load store instructions with long short format 24 LOCK0 165 low power systems 251 LRU algorit...

Page 606: ...area selection control register BPC 114 Peripheral I O 76 peripheral I O 74 Peripheral Status 106 PHCMD 105 PHS 106 Pin functions 33 40 Pin I O circuits 54 Pin Identification 28 pipeline 55 PLL synth...

Page 607: ...unter 306 Pulse width measurement 335 PWM 271 291 306 331 Q Quantization Error 543 R RAM 30 Reception buffer registers 372 Reception completion interrupt 374 Reception error interrupt 374 re initializ...

Page 608: ...71 Timer C control register 0 278 Timer C control register 1 280 Timer D counter Register 298 Timer Dn compare register 299 Timer Dn control register 301 Timer G capture compare registers with externa...

Page 609: ...lock frequency 355 Watch timer mode control register 350 watchdog timer 587 Watchdog timer clock selection register 359 Watchdog timer command register 361 Watchdog timer command status register 361 W...

Page 610: ...610 Preliminary User s Manual U15839EE1V0UM00...

Page 611: ...02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274...

Page 612: ......

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