8
µ
PD78F4225Y
3. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3-INTP6
PROGRAMMABLE
INTERRUPT
CONTROLLER
REAL-TIME
OUTPUT PORT
TIMER/COUNTER6
(8 BITS)
TIMER/COUNTER5
(8 BITS)
TIMER/COUNTER2
(8 BITS)
TIMER/COUNTER1
(8 BITS)
TIMER/COUNTER
(16 BITS)
WATCH TIMER
WATCHDOG TIMER
TI00
TI01
TO0
TI1
TO1
TI2
TO2
RTP0-RTP7
CLOCK OUTPUT
CONTROL
A/D
CONVERTER
AV
DD
AV
SS
PCL
BUZ
ANI0-ANI7
D/A
CONVERTER
ANO0
AV
SS
AV
REF1
ANO1
78K/IV
CPU CORE
FLASH
MEMORY
RAM
BAUD-RATE
GENERATOR
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
BUS I/F
UART/IOE1
RD
ASTB
WR
WAIT
AD0-AD7
A8-A15
A16-A19
PORT1
P10-P17
PORT0
P00-P05
PORT2
P20-P27
PORT3
P30-P37
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT12
P120-P127
PORT13
P130,P131
BUZZER OUTPUT
SYSTEM CONTROL
RESET
XT2
X1
XT1
X2
V
SS0
, V
SS1
V
DD0
, V
DD1
TEST/V
PP
CLOCKED
SERIAL
INTERFACE
BAUD-RATE
GENERATOR
UART/IOE2
EXA
Summary of Contents for uPD78F4225Y
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