NEC UPD789426 Series User Manual Download

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CHAPTER 12 SERIAL INTERFACE 20

User’s Manual U15075EJ2V1UD

226

(b) Asynchronous serial interface mode register 20 (ASIM20)

ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIM20 to 00H.

TXE20

Transmit operation control

Transmit operation stopped

Transmit operation enabled

Receive operation stopped

Receive operation enabled

RXE20

Receive operation control

TXE20

RXE20

PS201

PS200

CL20

SL20

ASIM20

<7>

<6>

Symbol

Address

After reset

R/W

FF70H

00H

R/W

Caution Bits 0 and 1 must be set to 0.

Summary of Contents for UPD789426 Series

Page 1: ...9426 PD789446 PD789435 PD789455 PD789436 PD789456 PD78F9436 PD78F9456 PD789426 789436 789446 789456 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U15075EJ2V1UD00 2nd editio...

Page 2: ...2 User s Manual U15075EJ2V1UD MEMO...

Page 3: ...including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken...

Page 4: ...emarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks...

Page 5: ...ety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death...

Page 6: ...nch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Squ...

Page 7: ...User s Manual U15075EJ2V1UD 7 MEMO...

Page 8: ...struction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To under...

Page 9: ...ser s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U14876E Language U14877E RA78K0S Assembler Package Structured Assembly Language...

Page 10: ...ges X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for S...

Page 11: ...UNCTIONS 37 2 1 List of Pin Functions 37 2 2 Description of Pin Functions 40 2 2 1 P00 to P03 Port 0 40 2 2 2 P10 P11 Port 1 40 2 2 3 P20 to P26 Port 2 40 2 2 4 P30 to P33 Port 3 41 2 2 5 P50 to P53 P...

Page 12: ...ddressing 70 3 4 1 Direct addressing 70 3 4 2 Short direct addressing 71 3 4 3 Special function register SFR addressing 72 3 4 4 Register addressing 73 3 4 5 Register indirect addressing 74 3 4 6 Base...

Page 13: ...Bit Timer 90 123 6 4 16 Bit Timer 90 Operation 127 6 4 1 Operation as timer interrupt 127 6 4 2 Operation as timer output 129 6 4 3 Capture operation 130 6 4 4 16 bit timer counter 90 readout 131 6 4...

Page 14: ...8 Bit A D Converter 197 CHAPTER 11 10 BIT A D CONVERTER PD789436 AND 789456 SUBSERIES 201 11 1 10 Bit A D Converter Functions 201 11 2 10 Bit A D Converter Configuration 201 11 3 10 Bit A D Converter...

Page 15: ...operation 278 14 4 3 Multiple interrupt servicing 279 14 4 4 Putting interrupt requests on hold 281 CHAPTER 15 STANDBY FUNCTION 282 15 1 Standby Function and Configuration 282 15 1 1 Standby function...

Page 16: ...NG CONDITIONS 337 APPENDIX A DEVELOPMENT TOOLS 340 A 1 Software Package 342 A 2 Language Processing Software 342 A 3 Control Software 343 A 4 Flash Memory Writing Tools 343 A 5 Debugging Tools Hardwar...

Page 17: ...Status Word Configuration 60 3 15 Stack Pointer Configuration 62 3 16 Data to Be Saved to Stack Memory 62 3 17 Data to Be Restored from Stack Memory 62 3 18 General Purpose Register Configuration 63...

Page 18: ...CPU Clock Crystal Ceramic Oscillation 117 5 11 Switching Between System Clock and CPU Clock RC Oscillation 118 6 1 Block Diagram of 16 Bit Timer 90 121 6 2 Format of 16 Bit Timer Mode Control Registe...

Page 19: ...ator Operation When CR60 N CRH60 M M N 168 7 21 Timing of Carrier Generator Operation When CR60 CRH60 N 169 7 22 Operation Timing in PWM Free Running Mode When Rising Edge Is Selected 171 7 23 Operati...

Page 20: ...211 11 10 Analog Input Pin Treatment 212 11 11 A D Conversion End Interrupt Request Generation Timing 213 11 12 AVDD Pin Handling 213 12 1 Block Diagram of Serial Interface 20 215 12 2 Block Diagram o...

Page 21: ...rogram Status Word 274 14 7 Format of Key Return Mode Register 00 275 14 8 Block Diagram of Falling Edge Detector 275 14 9 Flow from Generation of Non Maskable Interrupt Request to Acknowledgment 277...

Page 22: ...ing Example for Flash Writing Adapter Using 3 Wire Serial I O 302 17 9 Wiring Example for Flash Writing Adapter Using UART 303 A 1 Development Tools 341 B 1 Distance Between In Circuit Emulator and Co...

Page 23: ...3 Settings of Capture Edge 130 6 4 Buzzer Frequency of 16 Bit Timer 90 132 7 1 Operation Modes 137 7 2 8 Bit Timer Configuration 138 7 3 Interval Time of Timer 50 151 7 4 Interval Time of Timer 60 15...

Page 24: ...ller Driver 251 13 3 Frame Frequencies Hz 255 13 4 COM Signals 258 13 5 Select and Deselect Voltages COM0 to COM2 260 13 6 Select and Deselect Voltages COM0 to COM3 263 13 7 Output Voltages of VLC0 to...

Page 25: ...ation Minimum instruction execution time can be changed from high speed 0 5 s 4 0 MHz operation with main system clock to ultra low speed 122 s 32 768 kHz operation with subsystem clock RC oscillation...

Page 26: ...lash memory PD78F9456GB 8EU 64 pin plastic LQFP fine pitch 10 10 Flash memory PD789425GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM PD789426GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask...

Page 27: ...25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 CL1 X2 CL2 RESET P00 KR0 P01 KR1 P02 KR2...

Page 28: ...9 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 CL1 X2 CL2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CA...

Page 29: ...K20 Serial clock COM0 to COM3 Common output SI20 Serial input CPT90 Capture trigger input SO20 Serial output IC Internally connected TMI60 Timer input INTP0 to INTP3 External interrupt input TO90 TO50...

Page 30: ...nd A D converter 44 pin 30 pin 30 pin 30 pin 30 pin PD789124A PD789134A PD789177 PD789167 30 pin 30 pin PD789104A PD789114A PD789167 with enhanced A D converter 10 bits PD789104A with enhanced timer P...

Page 31: ...B to 24 KB 3 ch 1 ch 8 ch 31 PD789156 4 ch PD789146 8 KB to 16 KB 4 ch On chip EEPROM PD789134A 4 ch PD789124A 4 ch RC oscillation version PD789114A 4 ch Small scale package general purpose applicatio...

Page 32: ...8 ch 1 ch UART 1 ch 30 4 0 V PD789852 24 KB to 32 KB 3 ch 8 ch 3 ch UART 2 ch 31 On chip bus controller PD789850A 16 KB 1 ch 1 ch 1 ch 4 ch 2 ch UART 1 ch 18 4 0 V PD789861 RC oscillation version on...

Page 33: ...timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 CL1 X2 CL2 XT1 XT2 Interrupt control INTP0 P30 INTP1 P31 INTP2 P32 INTP3...

Page 34: ...d 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 CL1 X2 CL2 XT1 XT2 Interrupt control TO61 P33 BZO90 P21 Serial in...

Page 35: ...O 30 CMOS input 6 N ch open drain 4 Total 30 CMOS I O 20 CMOS input 6 N ch open drain 4 Timers 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converte...

Page 36: ...2 Operation mode External event counter 1 channel Timer outputs 1 1 2 Square wave outputs 1 2 Capture 1 input Function Interrupt sources 1 1 1 2 2 Notes 1 The watch timer can perform both watch timer...

Page 37: ...ort Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90...

Page 38: ...1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B8 PUB8 Input P90 to P97 Note I O Port 9 8 bit I O port Input output ca...

Page 39: ...Input P30 INTP0 TO50 Output 8 bit timer TM50 output Input P31 INTP1 TMI40 TO60 Output Input P32 INTP2 TO61 Output 8 bit timer TM60 output Input P33 INTP33 TMI60 Input External count clock input to ti...

Page 40: ...ified by setting pull up resistor option register 0 PU0 in port units 2 2 3 P20 to P26 Port 2 These pins constitute a 7 bit I O port In addition these pins enable buzzer output timer output serial int...

Page 41: ...register B3 PUB3 in 1 bit units 2 Control mode In this mode P30 to P33 function as timer I O and external interrupt input a TMI60 This is the external clock input pin to timer 60 b TO50 TO60 TO61 The...

Page 42: ...se of an on chip pull up resistor can be specified by setting pull up resistor option register B9 PUB9 in port units Note Only the PD789426 and PD789436 Subseries 2 2 10 S0 to S14Note These pins are s...

Page 43: ...ollowing ways Independently connect to a 10 k pull down resistor By using a jumper on the board connect directly to the dedicated flash programmer in the programming mode or to VSS in the normal opera...

Page 44: ...Input Independently connect to VSS via a resistor Output Leave open P50 to P53 Mask ROM version 13 W P50 to P53 Flash memory version 13 V I O Input Connect directly to VSS Output Leave this pin open...

Page 45: ...utput disable Input enable VDD P ch VDD P ch IN OUT N ch VSS VSS Output data Output disable IN OUT VDD N ch Middle voltage input buffer Input enable Pull up resistor mask option Type 8 A Type 17 Pull...

Page 46: ...Figure 3 1 Memory Map PD789425 789435 Special function registers 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 5 4 bits Reserved Reserved Internal ROM 12288 8 bits FFFFH FF00H FEFFH F...

Page 47: ...bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT tab...

Page 48: ...s Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table...

Page 49: ...bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT tab...

Page 50: ...bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT tab...

Page 51: ...s Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table...

Page 52: ...ry space 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an...

Page 53: ...is also used as a stack 2 LCD display RAM LCD display RAM is incorporated The LCD display RAM can also be used as ordinary RAM Each subseries incorporates LCD display RAM with the following capacity...

Page 54: ...ond to the particular function an area such as the special function registers are available Figures 3 7 through 3 12 show the data memory addressing modes Figure 3 7 Data Memory Addressing PD789425 78...

Page 55: ...gisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR...

Page 56: ...ters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR ad...

Page 57: ...gisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR...

Page 58: ...gisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR...

Page 59: ...ters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR ad...

Page 60: ...ber of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 00...

Page 61: ...rious interrupt sources IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is...

Page 62: ...stores data as shown in Figures 3 16 and 3 17 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 16 Data to Be Saved to Stack...

Page 63: ...in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names R0 to R7 and RP0 to RP...

Page 64: ...operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an...

Page 65: ...BH TCP90 Note 2 R Note 3 Undefined FF20H Port mode register 0 PM0 FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 R W FFH No...

Page 66: ...tor output control register 60 TCA60 W FF70H Asynchronous serial interface mode register 20 ASIM20 R W FF71H Asynchronous serial interface status register 20 ASIS20 R FF72H Serial operation mode regis...

Page 67: ...addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program c...

Page 68: ...ransferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any l...

Page 69: ...ed The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory T...

Page 70: ...struction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit...

Page 71: ...mer event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0...

Page 72: ...word This addressing is applied to the 256 byte space FF00H to FFFFH However the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description s...

Page 73: ...and format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC...

Page 74: ...he register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Descr...

Page 75: ...Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area...

Page 76: ...us methods of control Numerous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTION...

Page 77: ...TER 4 PORT FUNCTIONS User s Manual U15075EJ2V1UD 77 Figure 4 2 Port Types PD789446 789456 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 P20 P26 P65 Port 0 P70 P72 Port 7 Port 6 P50 P53 Po...

Page 78: ...port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90...

Page 79: ...specified by setting pull up resistor option register B9 PUB9 Input Note PD789426 789436 Subseries only 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Configuration...

Page 80: ...connected in 4 bit units by setting pull up resistor option register 0 PU0 Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 0 Figure 4 3 Block Di...

Page 81: ...ins on chip pull up resistors can be connected in 2 bit units by setting pull up resistor option register 0 PU0 This port is set in the input mode when the RESET signal is input Figure 4 4 shows a blo...

Page 82: ...interface I O buzzer output and timer output This port is set in the input mode when the RESET signal is input Figures 4 5 to 4 10 show block diagrams of port 2 Caution When using the pins of port 2...

Page 83: ...ock Diagram of P21 and P26 Internal bus VDD P ch P21 BZO90 P26 TO90 WRPUB2 RD WRPORT WRPM PUB21 PUB26 Output latch P21 P26 PM21 PM26 Alternate function Selector PUB2 Pull up resistor option register B...

Page 84: ...84 Figure 4 7 Block Diagram of P22 Internal bus VDD P ch P22 SS20 WRPUB2 RD WRPORT WRPM PUB22 Alternate function Output latch P22 PM22 Selector PUB2 Pull up resistor option register B2 PM Port mode r...

Page 85: ...Block Diagram of P23 Internal bus VDD P ch P23 ASCK20 SCK20 WRPUB2 RD WRPORT WRPM PUB23 Alternate function Output latch P23 PM23 Alternate function Selector PUB2 Pull up resistor option register B2 P...

Page 86: ...e 4 9 Block Diagram of P24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD P24 SO20 TxD20 WRPUB2 RD WRPORT WRPM PUB24 Alter...

Page 87: ...Figure 4 10 Block Diagram of P25 P25 SI20 RxD20 WRPUB2 RD WRPORT WRPM PUB25 Alternate function Output latch P25 PM25 VDD P ch Internal bus Selector PUB2 Pull up resistor option register B2 PM Port mod...

Page 88: ...t units by setting pull up resistor option register B3 PUB3 This port is also used as an external interrupt input capture input and timer I O This port is set in the input mode when the RESET signal i...

Page 89: ...3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 WRPUB3 RD WRPORT WRPM PUB31 to PUB33 PM31 to...

Page 90: ...p pull up resistor can be specified by a mask option This port is set in the input mode when the RESET signal is input Figure 4 13 shows a block diagram of port 5 Figure 4 13 Block Diagram of P50 to P...

Page 91: ...UD 91 4 2 6 Port 6 This is a 6 bit input only port This port is also used as the analog input of an A D converter Figure 4 14 shows a block diagram of Port 6 Figure 4 14 Block Diagram of Port 6 VREF R...

Page 92: ...ull up resistors can be connected in 1 bit units by setting pull up resistor option register B7 PUB7 This port is set in the input mode when the RESET signal is input Figure 4 15 shows a block diagram...

Page 93: ...port pins on chip pull up resistors can be connected in 1 bit units by setting pull up resistor option register B8 PUB8 This port is set in the input mode when the RESET signal is input Figure 4 16 s...

Page 94: ...rt pins on chip pull up resistors can be connected in 1 bit units by setting pull up resistor option register B9 PUB9 This port is set in the input mode when the RESET signal is input Figure 4 17 show...

Page 95: ...nput output in 1 bit units The port mode registers are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the registers to FFH When port pins are used as alternat...

Page 96: ...Symbol Address After reset 6 5 4 3 2 1 0 R W FF20H FF21H FF25H FFH FFH FFH R W R W R W 1 1 1 1 1 PM72 PM71 PM70 PM7 FF27H FFH R W 1 1 1 1 1 1 PM81 PM80 PM8Note FF28H FFH R W PM97 PM96 PM95 PM94 PM93...

Page 97: ...rt output latch 2 Pull up resistor option register 0 PU0 Pull up resistor option register 0 PU0 sets whether on chip pull up registers are used on ports 0 and 1 or not On the port specified to use an...

Page 98: ...ddress After reset R W FF32H 00H R W 7 6 5 4 3 2 1 0 PUB2n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 4 Pull up resistor option register B3 PUB3 Pull up resistor option...

Page 99: ...W 7 6 5 4 3 2 1 0 PUB7n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 6 Pull up resistor option register B8 PUB8 Note Pull up resistor option register B8 PUB8 sets whether...

Page 100: ...be used for the bits set in the output mode regardless of the setting of PUB9 This also applies to when the pins are used for alternate function PUB9 is set with a 1 bit or 8 bit memory manipulation i...

Page 101: ...the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of an output latch can be read by using a transfer instru...

Page 102: ...OP instruction or setting the processor clock control register PCC Main system clock oscillator RC oscillation mask option This circuit oscillates a frequency of 2 0 to 4 0 MHz Oscillation can be stop...

Page 103: ...8 bit timer 60 Watch timer LCD controller driver Clock to peripheral hardware CPU clock fCPU Standby controller Wait controller Selector STOP MCC PCC1 CLS CSS0 Internal bus Suboscillation mode registe...

Page 104: ...s Manual U15075EJ2V1UD 104 5 3 Registers Controlling Clock Generator The clock generator is controlled by the following registers Processor clock control register PCC Suboscillation mode register SCKM...

Page 105: ...s Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register PCC and the CSS0 flag in the subclock control register CSS Refer to 5 3 3 Subclock...

Page 106: ...selectionNote 0 0 0 0 0 0 FRC SCC SCKM Symbol Address After reset R W FFF0H 00H R W 7 6 5 4 3 2 1 0 FRC 0 1 On chip feedback resistor used On chip feedback resistor not used Control of subsystem cloc...

Page 107: ...00H Figure 5 4 Format of Subclock Control Register CPU clock operation status 0 0 CLS CSS0 0 0 0 0 CSS Address After reset R W FFF2H 00H R W 7 6 5 4 3 2 1 0 CLS 0 1 Operation based on the output of t...

Page 108: ...external circuit of the main system clock oscillator crystal ceramic oscillation Figure 5 5 External Circuit of Main System Clock Oscillator Crystal Ceramic Oscillation a Crystal or ceramic oscillati...

Page 109: ...o the XT1 pin and input the inverted signal to the XT2 pin Figure 5 7 shows the external circuit of the subsystem clock oscillator Figure 5 7 External Circuit of Subsystem Clock Oscillator a Crystal o...

Page 110: ...es of Incorrect Connection for Crystal Ceramic Oscillation 1 2 a Too long wiring b Crossed signal line VSS X1 X2 VSS X1 X2 PORTn n 0 to 3 5 to 9 c Wiring near high fluctuating current d Current flowin...

Page 111: ...75EJ2V1UD 111 Figure 5 8 Examples of Incorrect Connection for Crystal Ceramic Oscillation 2 2 e Signal is fetched VSS X1 X2 Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respecti...

Page 112: ...re 5 9 Examples of Incorrect Connection for RC Oscillation 1 3 a Too long wiring Main system clock Subsystem clock VSS CL2 CL1 XT1 XT2 VSS b Crossed signal line Main system clock Subsystem clock VSS C...

Page 113: ...luctuating current Main system clock Subsystem clock VSS CL2 CL1 High current XT1 XT2 VSS High current d Current flowing through ground line of oscillator potential at points A B and C fluctuates Main...

Page 114: ...en no subsystem clock is used If a subsystem clock is not necessary for example for low power consumption operation or clock operation handle the XT1 and XT2 pins as follows XT1 Connect to VSS XT2 Lea...

Page 115: ...clock selected In a system where no subsystem clock is used setting bit 1 FRC of the SCKM so that the on chip feedback resistor cannot be used reduces power consumption in STOP mode In a system where...

Page 116: ...ing Set Value After Switching CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 0 0 0 1 1 x 0 0 4 clocks 2fX fXT clocks 306 clocks 1 2 clocks fX 2fXT clocks 76 clocks 1 x 2 clocks 2 clocks Remarks 1 Two clocks...

Page 117: ...truction execution at the slow speed of the main system clock 1 6 s at 5 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed h...

Page 118: ...ain system clock 2 0 s at 4 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock...

Page 119: ...1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output can be controlled when a count value and compare value matches 3 Buzzer output Buzz...

Page 120: ...dware Table 6 1 16 Bit Timer 90 Configuration Item Configuration Timer counters 16 bits 1 TM90 Registers Compare register 16 bits 1 CR90 Capture register 16 bits 1 TCP90 Timer outputs 1 TO90 Control r...

Page 121: ...ter 90 TM90 16 bit compare register 90 CR90 fX 22 fX 26 fX 27 fXT CPT90 INTP0 P30 TOC90 TCL901TCL900 TOE90 F F TOD90 P26 Output latch P21 Output latch PM26 PM21 TO90 P26 INTTM90 BZO90 P21 Match OVF Bu...

Page 122: ...M90 TM90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input sets TM90 to 0000H Cautions 1 The count becomes undefin...

Page 123: ...bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode registers 2 3 PM2 PM3 Port 2 P2 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control regis...

Page 124: ...0 1 Timer output data inversion control Inversion disabled Inversion enabled TCL901 0 0 1 1 16 bit timer counter 90 count clock selection TCL900 0 1 0 1 TOE90 0 1 16 bit timer counter 90 output contro...

Page 125: ...4 88 kHz fcl 29 2 44 kHz fcl 210 1 22 kHz fcl 211 610 Hz fcl 212 305 Hz fcl 213 153 Hz fcl 24 4 88 kHz fcl 25 2 44 kHz fcl 28 305 Hz fcl 29 153 Hz fcl 210 76 Hz fcl 211 38 Hz fcl 212 19 Hz fcl 213 10...

Page 126: ...PM26 to 0 When using the P30 INTP0 CPT90 pin as a capture input set PM30 to 1 PM2 and PM3 are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 and PM3 to FFH Figure 6 4...

Page 127: ...t to 0 the capture operation is prohibited When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal INTTM90 is gene...

Page 128: ...2V1UD 128 Figure 6 6 Timing of Timer Interrupt Operation CR90 TM90 count value Count clock INTTM90 TO90 TOF90 N N N N N t 0000H N FFFFH N 0000H 0001H 0001H Interrupt acknowledgment Interrupt acknowled...

Page 129: ...1 0 1 0 1 1 0 1 0 1 1 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 Setting of count clock see Table 6 2 Inverse enable of timer output data TO90 output enable Caution If both the CPT901...

Page 130: ...detected and latches and retains the count value of 16 bit timer register 90 The TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6...

Page 131: ...M90 to 0000H and TM90 starts free running Figure 6 11 shows the timing of 16 bit timer counter 90 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation...

Page 132: ...uency see Table 6 4 Enables buzzer output Table 6 4 Buzzer Frequency of 16 Bit Timer 90 Buzzer Frequency BCS902 BCS901 BCS900 fcl fX 2 2 fcl fX 2 6 fcl fX 2 7 fcl fXT 0 0 0 fcl 2 4 78 1 kHz fcl 2 4 4...

Page 133: ...en the main system clock is stopped 2 The read function of TM90 uses the CPU clock for control refer to Figure 6 1 and reads an undefined value when the CPU clock is slower than the count clock values...

Page 134: ...Main system clock Oscillation stopped BZOE90 1 Buzzer output enabled At this time when the setting of P21 the buzzer output alternate function pin is PM21 0 P21 0 a square wave of the buzzer frequency...

Page 135: ...its first 3 Next rewrite the lower byte of CR90 16 bits 4 Clear the interrupt request flag TMIF90 5 After more than half the cycle of the count clock has passed from the start of the interrupt enable...

Page 136: ...put inversion Program example B When count clock 64 fX CPU clock fX TM90_VCT SET1 TMMK90 Timer interrupt disable CLR1 TMC90 3 Timer output inversion disable MOVW AX xxyyH CR90 rewrite value setting MO...

Page 137: ...8 bit timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer 40 only Square wave outp...

Page 138: ...mer output pin using software 7 2 8 Bit Timers 50 60 Configuration 8 bit timers 50 and 60 include the following hardware Table 7 2 8 Bit Timer Configuration Item Configuration Timer counters 8 bits 2...

Page 139: ...27 Timer 60 interrupt request signal from Figure 7 2 B Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode from Figure 7 2 C Cascade connectio...

Page 140: ...r 60 TCA60 TO61 INTP3 P33 Prescaler Selector Count operation start signal to timer 50 in cascade connection mode To Figure 7 1 D TM50 match signal in cascade connection mode TM60 timer counter match s...

Page 141: ...rite the CR50 with the TOE50 in a cleared status 2 If the valid edge of the count clock is selected for both edges in the PWM output mode TEG50 1 do not set 00H 01H and FFH to the CR50 If the rising e...

Page 142: ...value overflows ii TM60 After reset When TCE60 bit 7 of 8 bit timer mode control register 60 TMC60 is cleared to 0 When a match occurs between TM60 and CR60 When the TM60 count value overflows b Casca...

Page 143: ...put mode i TM50 After reset When the TCE50 flag is cleared to 0 When a match occurs between TM50 and CR50 When the TM50 count value overflows ii TM60 Reset When the TCE60 flag is cleared to 0 When a m...

Page 144: ...r 50 TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 Port mode register 3 PM3 Port 3 P3 1 8 bit timer mode control register 50 TMC50 8 bit timer mod...

Page 145: ...Hz 0 1 0 fX 2 7 39 1 kHz 0 1 1 fXT 32 768 kHz 1 0 0 Timer 60 match signal 1 0 1 Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode Other than...

Page 146: ...ascade connection mode the output signal of timer 60 is forcibly selected as the count clock 2 When operating TMC50 be sure to perform settings in the following order 1 Stop TM50 count operation 2 Set...

Page 147: ...nal input clock Other than above Setting prohibited TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Casc...

Page 148: ...manipulation instruction RESET input sets TCA60 to 00H Figure 7 6 Format of Carrier Generator Output Control Register 60 Symbol 7 6 5 4 3 2 1 0 Address After reset R W TCA60 0 0 0 0 0 RMC60 NRZB60 NR...

Page 149: ...clock and then rewrite TCA60 7 To enable operation in the carrier generator mode set a value to the compare registers CR50 CR60 and CRH60 and input the necessary value to the NRZB60 and NRZ60 flags i...

Page 150: ...operate 8 bit timer n0 as an interval timer settings must be made in the following sequence 1 Disable operation of 8 bit timer counter n0 TMn0 TCEn0 0 2 Disable timer output of TOn0 TOEn0 0 3 Set a c...

Page 151: ...of timer 60 output Input cycle of timer 60 output 2 8 Input cycle of timer 60 Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency Table 7 4 Interval Time o...

Page 152: ...01H N 00H 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Interval time Interval time Interval time Remarks 1 Interval time...

Page 153: ...0H 01H 00H 01H 00H FFH 00H 01H FFH FFH 00H Clear Clear Clear Count start Remark n 5 6 nm 50 60 61 Figure 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M...

Page 154: ...Clear Clear TMn0 overflows because M N CRn0 overwritten Remark n 5 6 nm 50 60 61 Figure 7 13 Timing of Interval Timer Operation with 8 Bit Resolution When Timer 60 Match Signal Is Selected for Timer...

Page 155: ...5 5 Set the operation mode of timer 60 to 8 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR60 7 Enable the operation of TM60 TCE60 1 Each time the valid edge is input the val...

Page 156: ...cleared to 00H and continues counting At the same time an interrupt request signal INTTMn0 is generated The square wave output is cleared to 0 by setting TCEn0 to 0 Tables 7 5 and 7 6 show the square...

Page 157: ...2 input cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 8 fTMI 2 3 input cycle Remark fX Main s...

Page 158: ...wing sequence 1 Disable operation of 8 bit timer counter 50 TM50 and 8 bit timer counter 60 TM60 TCE50 0 TCE60 0 2 Disable timer output of TO60 TOE60 0 3 Set the count clock for timer 60 see Table 7 7...

Page 159: ...0 1 fX 0 2 s 2 16 fX 13 1 ms 1 fX 0 2 s 0 0 1 2 2 fX 0 8 s 2 18 fX 52 4 ms 2 2 fX 0 8 s 0 1 0 fTMI input cycle fTMI input cycle 2 16 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 16 f...

Page 160: ...ulse TM50 00H X X 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H t Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generate...

Page 161: ...r 50 and timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1Note Note Start and clear of the timer in the...

Page 162: ...se TM50 00H X 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated be...

Page 163: ...d TM60 simultaneously match the values set in CR50 and CR60 respectively the TO60 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon...

Page 164: ...50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not matc...

Page 165: ...d Set P32 to the output mode PM32 0 set the P32 output latch to 0 and set TOE60 to output enable TOE60 1 If TO61 is selected Set P33 to the output mode PM33 0 set the P33 output latch to 0 and set TOE...

Page 166: ...n instruction must not be used Be sure to use an 8 bit memory manipulation instruction 4 While INTTM50 interrupt generated by the match signal of timer 50 is being output accessing TCA60 is prohibited...

Page 167: ...When CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 M 00H N 00H 01H N CRH60 M N 00H Carrier clock N 00H 00H N M 00H 01H L L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM...

Page 168: ...on When CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H N L CRH60 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1...

Page 169: ...n When CR60 CRH60 N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H 00H 00H N CRH60 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse...

Page 170: ...e operation mode of timer 50 to the PWM free running mode see Figure 7 4 5 Set the count clock for timer 50 6 Set P31 to the output mode PM31 0 and the P31 output latch to 0 and enable timer output of...

Page 171: ...verflow Overflow Count start Caution When the rising edge is selected do not set the CR50 to 00H If the CR50 is set to 00H PWM output may not be performed normally Figure 7 23 Operation Timing When Ov...

Page 172: ...0 TO50 N TM50 N 00H 00H 00H 01H FFH FFH 01H 01H 02H 01H Overflow Overflow Overflow Count start CR50 overwrite Overflow occurs but no change takes place because TO50 is high level Figure 7 24 Operation...

Page 173: ...1H 00H Overflow Overflow Overflow Count start Caution When both edges are selected do not set CR50 to 00H 01H and FFH If the CR50 is set to these values PWM output may not be performed normally Figure...

Page 174: ...ut of TO60 TOE60 1 7 Enable the operation of TM60 TCE60 1 The operation in the PWM output mode is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal IN...

Page 175: ...01H 01H M 00H Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when output is enabled TOE60 1 Figure 7 27 PWM Output Mode Timing When CR60 and CRH60 Are Overwritten Cou...

Page 176: ...d asynchronously to the count pulse Figure 7 28 Start Timing of 8 Bit Timer Counter Count pulse TMn0 count value 00H 01H 02H 03H 04H Timer start Remark n 5 6 2 Setting of 8 bit compare register n0 8 b...

Page 177: ...The watch and interval timers can be used at the same time Figure 8 1 is a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Cle...

Page 178: ...ified intervals Table 8 1 Interval Generated Using the Interval Timer Interval At fX 5 0 MHz At fX 4 19 MHz At fXT 32 768 kHz 2 4 1 fW 409 6 s 489 s 488 s 2 5 1 fW 819 2 s 978 s 977 s 2 6 1 fW 1 64 ms...

Page 179: ...mer count clock selection WTM7 Prescaler interval selection WTM6 0 0 0 0 1 1 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 Control o...

Page 180: ...p to 29 1 fW seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval timer...

Page 181: ...d 5 bit counter operation is enabled by setting bit 0 WTM0 of the watch mode timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register i...

Page 182: ...ay When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Runaway Detection Time Runaway Detection Time At fX 5 0 MHz 2 11 1 fX 410 s 2 13 1...

Page 183: ...atchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bit...

Page 184: ...anipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Select Register WDCS2 0 0 1 1 WDCS1 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kHz...

Page 185: ...2 Starts reset operation upon overflow occurrence 0 0 RUN 0 0 WDTM4 WDTM3 0 0 0 WDTM 7 6 5 4 Symbol Address After reset R W FFF9H 00H R W 3 2 1 0 Notes 1 Once RUN has been set 1 it cannot be cleared...

Page 186: ...nd the runaway detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT mo...

Page 187: ...pt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT...

Page 188: ...g inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 10 2 8 Bit A D Converter...

Page 189: ...voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the c...

Page 190: ...ersion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied to...

Page 191: ...e 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 FR00 0 1 0 0 1 0 Other than above Conversion dis...

Page 192: ...is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADS0 to 00H Figure 10 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol Ad...

Page 193: ...AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 6 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resisto...

Page 194: ...sion is canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 10 4 2 Input voltage and conversion re...

Page 195: ...S User s Manual U15075EJ2V1UD 195 Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D conversion result ADCR0 1 512 1 256 3 512 2 256 5 512 3 256 50...

Page 196: ...ied in analog input channel specification register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt reque...

Page 197: ...o a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion resul...

Page 198: ...operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8...

Page 199: ...on do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion cou...

Page 200: ...to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same voltag...

Page 201: ...g inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 11 2 10 Bit A D Converter...

Page 202: ...R sends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 is a 16 bit register that holds the result of A D conversion The lower 6 bits are fixed to...

Page 203: ...the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated...

Page 204: ...ote 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 FR00 0 1 0 0 1 0 Other than above Conversion d...

Page 205: ...is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 11 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol...

Page 206: ...AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resist...

Page 207: ...anceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 11 4 2 Input voltage and conversion result The...

Page 208: ...Manual U15075EJ2V1UD 208 Figure 11 5 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 A D conversion result ADCR0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 20...

Page 209: ...n specified in A D input selection register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request sign...

Page 210: ...to a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion resu...

Page 211: ...operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 11 8 and 11 9 show the timing at which the conversion result is read Figure 11 8...

Page 212: ...ion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion co...

Page 213: ...to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same volta...

Page 214: ...As it supports simultaneous transmission and reception 3 wire serial I O mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial I O m...

Page 215: ...ift clock SI20 P25 RxD20 SO20 P24 TxD20 4 Parity detection Stop bit detection Reception data counter Parity operation Stop bit addition Transmission data counter SL20 CL20 PS200 PS201 Reception enable...

Page 216: ...eception buffer register 20 RXB20 RXB20 holds a reception data A new reception data is transferred from reception shift register 20 RXS20 every 1 byte data reception When the data length is seven bits...

Page 217: ...n control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB C...

Page 218: ...reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable RXE20 0 1 Receive operation control Receive operation stop Receive operation enable PS201 0 0 1 1 Parity bit s...

Page 219: ...ck SCK20 output 0 1 External clock SCK20 input 0 0 1 1 1 Note 2 Note 2 0 1 0 1 LSB Internal clock SI20Note 2 SO20 CMOS output SCK20 output Other than above Setting prohibited 3 Asynchronous serial int...

Page 220: ...No parity error has occurred A parity error has occurred when the transmit parity and receive parity did not match FE20 0 1 Flaming error flag No framing error has occurred A framing error has occurre...

Page 221: ...ohibited 2 5 MHz 1 25 MHz 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz Other than above TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Note An external clock can be used onl...

Page 222: ...e of a clock generated from the system clock is estimated by using the following expression Baud rate bps fX Main system clock oscillation frequency n Value determined by the settings of TPS200 to TPS...

Page 223: ...Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 19 200 307 2 31 250 50...

Page 224: ...20 and P25 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20...

Page 225: ...tion instruction RESET input sets ASIM20 to 00H TXE20 0 1 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled RXE20 0 1...

Page 226: ...at the desired baud rate In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate th...

Page 227: ...pecification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial...

Page 228: ...0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive operation control PS201 Par...

Page 229: ...No overrun error has occurred An overrun error has occurredNote 2 when the next receive operation is completed before data is read from reception buffer register 20 FE20 0 1 0 1 Framing error flag Ov...

Page 230: ...bove TPS203 TPS202 TPS201 TPS200 0 0 0 0 BRGC20 7 6 5 4 Symbol Address After reset R W FF73H 00H R W 3 2 1 0 Note Can only be used in the UART mode Cautions 1 When writing to BRGC20 during a communica...

Page 231: ...ock generated from the system clock is estimated by using the following expression Baud rate bps fX Main system clock oscillation frequency n Values determined by the settings of TPS200 to TPS203 as s...

Page 232: ...he baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate bps fASCK Frequency of clock input to ASCK20 pin Table 12 6 Relationsh...

Page 233: ...Transmit Receive Data D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Start bit One data frame Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits...

Page 234: ...parity bit is counted and if the number is odd a parity error occurs ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value of...

Page 235: ...Transmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 Caution Do...

Page 236: ...ted after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to reception buffer register 20 RXB20 and a r...

Page 237: ...t Table 12 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next...

Page 238: ...it 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception reception buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as follows Parity Rx...

Page 239: ...ked serial interface such as the 75XL Series 78K Series and 17K Series Communication is performed using three lines a serial clock SCK20 serial output SO20 and serial input SI20 1 Register setting 3 w...

Page 240: ...ternal clock input to the SCK20 pinNote Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase selection Outputs at the falling edge of SCK20 O...

Page 241: ...eive operation enabled RXE20 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error occurs Odd parity Even parity Receive oper...

Page 242: ...When writing to BRGC20 during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communicatio...

Page 243: ...hen transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in the reception buffer register RXB20 SIO20 on the rise of SCK20 At the end...

Page 244: ...0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last bit previously output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0...

Page 245: ...0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK20 SO20 SI20 SIO20 write INTCSI20 v Slave operation when DAP20 0 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SC...

Page 246: ...e SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 SO...

Page 247: ...20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3...

Page 248: ...O6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SO20 SI20 SIO20 write INTCSI20 DI0 DO0 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20...

Page 249: ...until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS20 SIO20 when the follow...

Page 250: ...nt Outputs and Maximum Number of Pixels Bias Method Time Slots Common Signals Used Maximum Number of Segments Maximum Number of Pixels 3 COM0 to COM2 15 5 segments 3 commons PD789426 789436 Subseries...

Page 251: ...LC1 VAON0 3 2 1 0 3 2 1 0 6 5 7 4 FA05H LCDON0 S5 LCDM00 LCD clock control register 0 LCDC0 LCD display mode register 0 LCDM0 LCD clock selector Clock generator for boosting Selector Prescaler Booster...

Page 252: ...LCD clock control register 0 LCDC0 LCD voltage amplification control register 0 LCDVA0 1 LCD display mode register 0 LCDM0 LCDM0 specifies whether to enable display operation It also specifies the ope...

Page 253: ...mode 1 3 1 3 Note When the LCD display panel is not used the VAON0 and LIPS0 must be set to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to 0 2 When operating VAON0 follow th...

Page 254: ...29 fXT 32 768 kHz fX 25 156 3 kHz fX 26 78 1 kHz fX 27 39 1 kHz Note Specify an LCD source clock fLCD frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDC0 s...

Page 255: ...oltage Amplification Control Register 0 0 GAIN LCDVA0 Symbol Address After reset R W FFB3H 00H R W 7 6 5 4 3 2 1 0 GAIN 0 1 1 5 times specification of the LCD panel used is 4 5 V 1 0 times specificati...

Page 256: ...ential 7 Start output corresponding to each data memory by setting LCDON0 bit 7 of LCDM0 LCDON0 1 13 5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA0EH Data in...

Page 257: ...als The segment signals correspond to LCD display data memory Bits 0 1 2 and 3 of each byte are read in synchronization with COM0 COM1 COM2 and COM3 respectively If the contents of each bit are 1 it i...

Page 258: ...signals Figure 13 6 Common Signal Waveforms COMn Three time slot mode TF 3 T VLC0 VSS VLCD VLC1 VLC2 TF 4 T COMn Four time slot mode VLC0 VLCD VLC1 VLC2 VSS T One LCD clock period TF Frame frequency...

Page 259: ...sary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13 5 at the timing of the common signals COM0 to COM2 Table 13 5 Select and Deselect Voltages COM0 to COM2 Segment...

Page 260: ...1 1 0 0 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 COM 3 COM 2 COM 1 COM...

Page 261: ...Figure 13 10 Three Time Slot LCD Drive Waveform Examples VLC0 VLC2 COM0 VLCD 0 COM0 S6 VLCD VLC1 1 3VLCD 1 3VLCD VSS0 VLC0 VLC2 COM1 VLC1 VSS0 VLC0 VLC2 COM2 VLC1 VSS0 VLC0 VLC2 S6 VLC1 VSS0 VLCD 0 CO...

Page 262: ...y to apply the select or deselect voltage to the S2 and S3 pins according to Table 13 6 at the timing of the common signals COM0 to COM3 Table 13 6 Select and Deselect Voltages COM0 to COM3 Segment Co...

Page 263: ...r Time Slot LCD Panel 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD pane...

Page 264: ...me Slot LCD Drive Waveform Examples Remark The waveforms of COM2 S2 and COM3 S2 are omitted TF VLC0 VLC2 COM0 VLCD 0 COM0 S2 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 V...

Page 265: ...equires an external capacitor recommended value 0 47 F because it employs a capacitance division method to generate a supply voltage to drive the LCD Table 13 7 Output Voltages of VLC0 to VLC2 Pins LC...

Page 266: ...ed One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt This interrupt undergoes mask control If two or more interrupts with the same priority...

Page 267: ...f serial interface 20 UART transmission 0012H 7 INTWTI Interval timer interrupt 0014H 8 INTTM90 Generation of match signal of 16 bit timer 90 0016H 9 INTTM50 Generation of match signal of 8 bit timer...

Page 268: ...le interrupt MK IF IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 INTM1 KRM00 Interrupt request Edge...

Page 269: ...y return mode register 00 KRM00 Table 14 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 14 2 Flags Corresponding to Interrupt Reque...

Page 270: ...set to 0 2 The WDTIF flag is R W enabled only when a watchdog timer is used as an interval timer If the watchdog timer mode 1 or 2 is used set the WDTIF flag to 0 3 Because port 3 has an alternate fun...

Page 271: ...read when the watchdog timer is used in watchdog timer mode 1 or 2 its value becomes undefined 3 Because port 3 has an alternate function as the external interrupt input when the output level is chang...

Page 272: ...1 0 1 0 1 Symbol Address After reset INTP0 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection Falling edge Rising edge Setting p...

Page 273: ...able interrupts After that clear 0 PIF3 then set PMK3 to 0 to enable interrupts 5 Program status word PSW The program status word is a register used to hold the instruction execution result and the cu...

Page 274: ...MK1 KRMK00 1 to disable interrupts After setting KRM00 clear KRMK00 after clearing bit 6 of IF1 KRIF00 0 to enable interrupts 3 When P00 to P03 are in input mode on chip pull up resistors are connect...

Page 275: ...tack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 14 9 shows the flow from non maskable interrupt request ge...

Page 276: ...nerated Interrupt servicing starts WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 14 10 Timing of Non Maskable Interrupt Request Acknowledgment...

Page 277: ...clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specificatio...

Page 278: ...n Final Clock Under Execution Clock CPU NOP MOV A r Saving PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks If the interrupt request flag XXIF is generated in...

Page 279: ...uest is acknowledged the EI instruction is issued and the interrupt request is enabled Example 2 Multiple interrupts are not performed because interrupts are disabled INTyy EI Main servicing RETI INTy...

Page 280: ...rupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending ins...

Page 281: ...entire system The power consumption of the CPU can be substantially reduced in this mode The data memory can be retained at the low voltage VDD 1 8 V Therefore this mode is useful for retaining the c...

Page 282: ...illation stabilization time is fixed to 27 fCC Figure 15 1 Format of Oscillation Stabilization Time Select Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1...

Page 283: ...bit timer Operation enabled Operation stopped TM50 Operation enabled Note 1 8 bit timer TM60 Operation enabled Operation enabled Note 2 Watch timer Operation enabled Operation enabled Note 3 Operation...

Page 284: ...executed Figure 15 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken line indicates t...

Page 285: ...on RESET signal Wait 215 fX 6 55 ms Reset period HALT mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remark fX Main system clo...

Page 286: ...stem Clock Is Running Item While the subsystem clock is running While the subsystem clock is not running Main system clock Oscillation stopped CPU Operation stopped Port output latch Remains in the st...

Page 287: ...ed interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt is disabled the instruction at the next address is executed Figure 15 4 Releasing STOP Mode b...

Page 288: ...t STOP instruction RESET signal Wait STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Reset period Remark fX Main system cl...

Page 289: ...during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization time...

Page 290: ...rflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation continues Normal operation reset processing Oscillation stabi...

Page 291: ...Capture register TCP90 Undefined 16 bit timer Buzzer output control register BZC90 00H Timer counter TM50 TM60 00H Compare register CR50 CR60 CRH60 Undefined Mode control register TMC50 TMC60 00H 8 bi...

Page 292: ...atus After Reset Display mode register LCDM0 00H Clock control register LCDC0 00H LCD controller driver Voltage amplification control register LCDVA0 00H Request flag register IF0 IF1 00H Mask flag re...

Page 293: ...Item PD78F9436 PD78F9456 PD789425 789435 PD789426 789436 PD789445 789455 PD789446 789456 ROM 12 KB 16 KB 12 KB 16 KB 12 KB 16 KB High speed RAM 512 bytes Internal memory LCD display RAM 5 4 bits 15 4...

Page 294: ...ocontroller is solder mounted on the target system Distinguishing software facilities small quantity varied model production Easy data adjustment when starting mass production 17 1 1 Programming envir...

Page 295: ...to 76 800 bps Notes 2 4 5 MHz Note 5 4 91 or 5 MHz Note 2 1 0 RxD20 SI20 P25 TxD20 SO20 P24 8 Notes 1 Selection items for TYPE settings on the dedicated flash programmer Flashpro III part no FL PR3 PG...

Page 296: ...F9456 Notes 1 When supplying the system clock from a dedicated flash programmer connect the CLK and X1 pins and cut off the resonator on the board When using the clock oscillated by the on board reson...

Page 297: ...Function Pin Name 3 Wire Serial I O UART VPP1 Output Write voltage VPP VPP2 VDD I O VDD voltage generation voltage monitoring VDD Note Note GND Ground VSS CLK Output Clock output X1 RESET Output Reset...

Page 298: ...connect the VPP pin as follows 1 Connect a pull down resistor of RVPP 10 k to the VPP pin 2 Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND The fol...

Page 299: ...lash programmer Other device Input pin 2 Malfunction of another device When the dedicated flash programmer output or input is connected to a serial interface pin input or output connected to another d...

Page 300: ...except those used for flash memory programming communication to the status immediately after reset Therefore if the external device does not acknowledge an initial status such as the output high impe...

Page 301: ...flash writing is used Figure 17 8 Wiring Example for Flash Writing Adapter Using 3 Wire Serial I O PD78F9436 GND VDD VDD2 LVDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V G...

Page 302: ...er Using UART PD78F9436 GND VDD VDD2 LVDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 3...

Page 303: ...ns Pull up resistor The connection of on chip pull up resistors for port 5 I O port can be switched in 1 bit units 1 Pull up resistor is connected 2 Pull up resistor is not connected RC oscillation RC...

Page 304: ...cification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register ide...

Page 305: ...flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in...

Page 306: ...A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte x x x A PSW 2 4 A PSW PSW A 2 4 PSW A x x x A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byt...

Page 307: ...L byte 2 6 A CY A HL byte x x x ADDC A byte 2 4 A CY A byte CY x x x saddr byte 3 6 saddr CY saddr byte CY x x x A r 2 4 A CY A r CY x x x A saddr 2 4 A CY A saddr CY x x x A addr16 3 8 A CY A addr16...

Page 308: ...r saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x OR A byte 2 4 A A byte x saddr byte 3 6 saddr saddr byte x A r 2 4 A A r...

Page 309: ...x DEC r 2 4 r r 1 x x saddr 2 4 saddr saddr 1 x x INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 x ROL A 1 1 2 CY A0 A7 Am 1 Am 1 x RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 x ROLC A...

Page 310: ...ddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jd...

Page 311: ...e addr1 6 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH M...

Page 312: ...te saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd...

Page 313: ...314 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions...

Page 314: ...n 30 mA Output current low IOL Total for all pins 160 mA During normal operation 40 to 85 C Operating ambient temperature TA During flash memory programming 10 to 40 C Mask ROM version 65 to 150 C Sto...

Page 315: ...um ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are...

Page 316: ...istics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillator wire as follows in the area enclo...

Page 317: ...the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the gro...

Page 318: ...the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal...

Page 319: ...0 0 3VDD V VIL1 P10 P11 P60 to P65 P70 to P72 P80 Note P81 Note P90 to P97 Note VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0 0 3VDD V VIL2 P50 to P53 VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0...

Page 320: ...VO VDD 3 A Output leakage current low ILOL VO 0 V 3 A Software pull up resistor R1 VI 0 V P00 to P03 P10 P11 P20 to P26 P30 to P33 P70 to P72 P80 Note 1 P81 Note 1 P90 to P97 Note 1 50 100 200 k Mask...

Page 321: ...g mode Note 7 C1 C2 22 pF VDD 2 0 V 10 Note 3 0 6 1 25 mA VDD 5 0 V 10 1 65 3 0 mA VDD 3 0 V 10 0 65 1 44 mA IDD7 4 0 MHz RC oscillation operation mode R 4 7 k C 22 pF VDD 2 0 V 10 0 38 1 05 mA VDD 5...

Page 322: ...VDD 5 0 V 10 0 1 17 A VDD 3 0 V 10 0 05 5 5 A IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 5 A VDD 5 0 V 10 Note 2 5 2 10 8 mA VDD 3 0 V 10 Note 3 1 4 3 8 mA Power supply current Note 1 PD78F9436 78F945...

Page 323: ...em clock 114 122 125 s Capture input high low level width tCPTH tCPTL CPT90 10 s VDD 2 7 to 5 5 V 0 4 MHz TMI60 input frequency fTMI VDD 1 8 to 5 5 V 0 275 kHz VDD 2 7 to 5 5 V 0 1 s TMI60 input high...

Page 324: ...wire serial I O mode external clock input Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns SCK20 cycle time tKCY2 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns SCK20 high low l...

Page 325: ...arameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns ASCK20 cycle time tKCY3 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns ASCK20 high low level width tKH3 tKL3 VDD 1 8 to 5 5 V 1600...

Page 326: ...1 inputs 0 8VDD 0 2VDD Point of measurement 0 8VDD 0 2VDD Clock Timing 1 fX tXL tXH X1 CL1 input VIH4 MIN VIL4 MAX 1 fXT tXTL tXTH XT1 input VIH5 MIN VIL5 MAX Capture Input Timing CPT90 tCPTL tCPTH TM...

Page 327: ...iming RESET tRSL Serial Transfer Timing 3 wire serial I O mode tKCYm tKLm tKHm SCK20 tSIKm tKSIm tKSOm Input data Output data SI20 SO20 Remark m 1 2 3 wire serial I O mode when using SS20 tKAS2 SO20 S...

Page 328: ...ameter Symbol Conditions MIN TYP MAX Unit Resolution 10 10 10 bit 4 5 V AVDD 5 5 V 0 2 0 4 FSR 2 7 V AVDD 4 5 V 0 4 0 6 FSR Overall error Note 1 8 V AVDD 2 7 V 0 8 1 2 FSR 4 5 V AVDD 5 5 V 14 100 s 2...

Page 329: ...O 5 A 0 0 2 V LCD output voltage differential Note 3 segment VODS IO 1 A 0 0 2 V Notes 1 This is a capacitor that is connected between voltage pins used to drive the LCD C1 A capacitor connected betwe...

Page 330: ...Stabilization Wait Time TA 40 to 85 C VDD 1 8 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit Crystal ceramic oscillation 2 15 fX s Release by RESET RC oscillation 2 7 fCC s Crystal ceramic osci...

Page 331: ...mA Write current Note VPP pin IPPW When VPP supply voltage VPP1 12 mA Erase current Note VDD pin IDDE When VPP supply voltage VPP1 During fX 5 0 MHz operation 7 mA Erase current Note VPP pin IPPE When...

Page 332: ...the characteristics curves of the time from the start of voltage amplification VAON0 1 and the changes in the LCD output voltage when GAIN is set as 1 using the 3 V display panel 5 5 5 4 5 4 3 5 3 2 5...

Page 333: ...lowing shows the temperature characteristics curves of LCD output voltage LCD output voltage V VLCD2 VLCD1 VLCD0 VLCD2 VLCD1 VLCD0 40 30 20 10 0 10 20 30 40 50 60 70 80 40 30 20 10 0 10 20 30 40 50 60...

Page 334: ...C 12 0 0 2 D F 1 125 14 0 0 2 B 12 0 0 2 N 0 10 P Q 0 1 0 05 1 0 S R 3 4 3 R H K J Q G I S P detail of lead end NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum...

Page 335: ...STIC LQFP 10x10 ITEM MILLIMETERS A B D G 12 0 0 2 10 0 0 2 1 25 12 0 0 2 H 0 22 0 05 C 10 0 0 2 F 1 25 I J K 0 08 0 5 T P 1 0 0 2 L 0 5 P 1 4 Q 0 1 0 05 T 0 25 S 1 5 0 10 U 0 6 0 15 S64GB 50 8EU 2 R 3...

Page 336: ...lastic TQFP 12 12 PD789456GK 9ET 64 pin plastic TQFP 12 12 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210...

Page 337: ...350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 3 PD78F9436GK 9ET 64 pin plastic TQFP 12 12 PD78F9456GK 9ET 64 pin plastic T...

Page 338: ...10 PD789446GB 8EU A 64 pin plastic LQFP 10 10 PD789455GB 8EU A 64 pin plastic LQFP 10 10 PD789456GB 8EU A 64 pin plastic LQFP 10 10 PD78F9436GK 9ET A 64 pin plastic TQFP 12 12 PD78F9456GK 9ET A 64 pin...

Page 339: ...ies Figure A 1 shows development tools Support to PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in PC98 NX Series When using the PC98 NX Series...

Page 340: ...Language processing software Debugging software Control software Host machine PC or EWS Interface adapter Flash memory writing tools Flash programmer In circuit emulator Power supply unit Emulation bo...

Page 341: ...age RA78K0S Assembler package Part number S RA78K0S Program that converts program written in C language into object codes that can be executed by a microcontroller Used in combination with an assemble...

Page 342: ...r Control software provided for efficient user program development in the Windows environment The project manager allows a series of tasks required for user program development to be performed includi...

Page 343: ...A Interface adapter Adapter required when using a personal computer incorporating the PCI bus as the host machine IE 789456 NS EM1 Emulation board Emulation board for emulating the peripheral hardwar...

Page 344: ...e simulating the operation of the target system on the host machine Using SM78K0S the logic and performance of the application can be verified independently of hardware development Therefore the devel...

Page 345: ...nd TGK 064SBW are products of TOKYO ELETECH CORPORATION Table B 1 Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter...

Page 346: ...ion probe NP 64GB TQ Emulation board IE 789456 NS EM1 22 mm 40 mm 34 mm Target system Conversion adapter TGB 064SDP 16 mm 16 mm 11 mm Figure B 3 Connection Conditions of Target System When NP H64GB TQ...

Page 347: ...Emulation board IE 789456 NS EM1 Conversion adapter TGK 064SBW Target system CN1 Emulation probe NP 64GK NP H64GK TQ Note Distance when NP 64GK is used When NP H64GK TQ is used the distance is 370 mm...

Page 348: ...ual U15075EJ2V1UD 349 Figure B 6 Connection Conditions of Target System When NP H64GK TQ Is Used Emulation probe NP H64GK TQ Emulation board IE 789456 NS EM1 42 mm 45 mm 18 4 mm 11 mm Target system Co...

Page 349: ...ntrol register 60 TCA60 148 E 8 bit compare register 50 CR50 141 8 bit compare register 60 CR60 141 8 bit compare register H60 CRH60 141 8 bit timer counter 50 TM50 142 8 bit timer counter 60 TM60 142...

Page 350: ...r option register B2 PUB2 98 Pull up resistor option register B3 PUB3 98 Pull up resistor option register B7 PUB7 99 Pull up resistor option register B8 PUB8 99 Pull up resistor option register B9 PUB...

Page 351: ...R60 8 bit compare register 60 141 CR90 16 bit compare register 90 122 CRH60 8 bit compare register H60 141 CSIM20 Serial operation mode register 20 218 225 228 241 CSS Subclock control register 107 I...

Page 352: ...ter B3 98 PUB7 Pull up resistor option register B7 99 PUB8 Pull up resistor option register B8 99 PUB9 Pull up resistor option register B9 100 R RXB20 Receive buffer register 20 217 S SCKM Suboscillat...

Page 353: ...mer Mode Control Register 50 Modification of Figure 7 5 Format of 8 Bit Timer Mode Control Register 60 Addition of Cautions to Figure 7 6 Format of Carrier Generator Output Control Register 60 Modific...

Page 354: ...CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Total revision of appendix APPENDIX A DEVELOPMENT TOOLS Addition of appendix APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX D REVISION HISTORY Deletion o...

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